FPGA companies will design supercomputer

July 1, 2005
Designers of military computing platforms praise field-programmable gate arrays (FPGAs) for their efficiency with space and power, but they often choose competing solutions like digital signal processors (DSPs) because FPGAs are so difficult to program.

By Ben Ames

EDINBURGH, Scotland - Designers of military computing platforms praise field-programmable gate arrays (FPGAs) for their efficiency with space and power, but they often choose competing solutions like digital signal processors (DSPs) because FPGAs are so difficult to program.

Now a consortium of computer companies is trying to change that.

In May, a group of technology companies and academics launched the FPGA High Performance Computing Alliance (FHPCA). Over the next two years, they will design and build a 64-node, FPGA-based super computer, capable of achieving processing speeds in excess of one trillion floating-point operations per second (1 TeraFLOPS).

“In the FPGA world, there is a growing interesting in military and aerospace, both on the front end for I/O and for high-performance general processing. FPGAs can save space and power compared to traditional solutions,” says Allan Cantle, chief executive officer of Nallatech in Edinburgh, Scotland, one of the consortium members.

“But FPGAs are not the easiest things in the world to program. We need to make it easier for the customer to use,” he says.

The Virtex-4 FX60 from Xilinx is a 90-nanometer FPGA with integrated serial transceivers from 622 megabits per second to 10.3125 gigabits per second. It is for high-speed serial applications such as servers, storage subsystems, communication line cards, and backplanes.
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“The ability to program these requires a balance between software and hardware expertise; parallel programming. We will educate the market to see they can make significantly higher performance, both in the embedded and the high performance computing (HPC) environment,” Cantle says. “We will provide a system with reference designs, so people can experiment themselves at a relatively low cost.”

The Edinburgh Parallel Computing Centre (EPCC) at the University of Edinburgh will own the new supercomputer. Experts will build the computer using commercial-off-the-shelf (COTS) technology from alliance members.

To demonstrate the system’s power and flexibility, the alliance will select and port three existing supercomputer applications from science and industry in June 2005.

Eventually, visiting researchers will be able to arrange access to the FHPCA system for three-month research programs. Alliance members will then port their applications to the system.

FHPCA group members include:

  • Xilinx of San Jose, Calif.;
  • Nallatech of Edinburgh, Scotland;
  • the Institute for System Level Integration (ISLI) at the Alba Centre in Livingston, England;
  • the Edinburgh Parallel Computing Centre (EPCC) at the University of Edinburgh;
  • Alpha Data of Edinburgh; and
  • Algotronix of Edinburgh.

Together, they have raised a budget of £3.6 million (equal to US$6.6 million) for the alliance, including £1.345 (US$2.5 million) from Scottish Enterprise.

The supercomputer will use DIMEtalk for control, and RapidIO as the high-speed switched-network fabric to join the FPGAs, says Malachy Devlin, chief technology officer at Nallatech.

“PCI Express and StarFabric consume an awful lot of real estate on an FPGA; they take up many gates, taking away crucial silicon we would rather use for computation,” he says.

Nallatech engineers created DIMEtalk, an FPGA connectivity design tool, which shortens development time with a software application for system communications. It enables developers to design packet-based communications networks across multiple FPGAs. The term is an acronym for DSP and image-processing module for advanced FPGAs.

“You always hear that FPGAs can provide any architecture to fit your problem. Now it is true also on the network level,” Devlin says.

The alliance will use FPGA processors solely because they offer so much power. FPGA-based computing is currently used for high-performance applications such as military signal processing, high-speed machine vision, and bioinformatics.

The processing demands of these tasks are difficult to meet using conventional microprocessor-based technology, but FPGA-based computers are by their nature massively parallel, performing many calculations per clock cycle and achieving very high data throughput. One reason is that FPGA chips are typically able to dedicate many more pins to input/output than a microprocessor.

“FPGA computing is today where conventional microprocessor-based computing was 15 years ago,” Cantle says.

“The potential exists to deliver unprecedented computational capacity using less power in a smaller space; however, to unleash that potential the industry needs to develop the means to give users low risk access to that power,” Cantle says. “Working with the FHPCA will help industry to begin the process of opening up the technology to a wider range of users and hence applications through education, the development of standardized tools and providing a platform for large-scale demonstrations.”

The BenNUEY-PCI-4E is an FPGA-based computing card from Nallatech for network applications such as intrusion detection, content processing, and data encryption. It can host as many as four Xilinx Virtex-II Pro FPGAs, four Gigabit Ethernet ports, a PCI interface, and four RocketIO channels for intercard communications.
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The effort is unique, says Mark Parsons, EPCC’s commercial director. “What’s really exciting about this project is that no one’s ever tried to build a big supercomputer with these chips before. People are always thinking up interesting designs, but the supercomputer we’ve come up with is an absolutely unique system. We’re trying to join a whole lot of these high-performance chips together so we can tackle very large and complex problems. It’s a real opportunity for Scotland to take the lead in a hugely exciting area.”

The use of FPGAs in high-performance computing brings superior performance for many important classes of problems, says Patrick Lysaght, senior director of Xilinx Research Labs and the Xilinx University Program.

“The key to this improvement is to use arrays of FPGAs instead of older architectures based on sequential computers. The natural concurrency of the algorithms can be best exploited by mapping them to FPGAs with all the advantages of highly specialized data paths, customized memory interfaces and optimized interconnection topologies. The tremendous flexibility of Xilinx FPGAs makes it possible to create a custom computing environment for each class of problem.”

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