Up next: through-silicon vias

There are several ways to achieve three-dimensional shrinkage in electronics assembly.

By Keith Gurnett and Tom Adams

There are several ways to achieve three-dimensional shrinkage in electronics assembly. Stacking chips within one package, which has been a production reality for several years, accomplishes two goals: a smaller form factor and improved performance. Stacking chip packages–the “package-on-package’ technique–and embedding thinned active devices also save some space and enhance performance by shortening interconnect distances.

One of the hottest current buzzwords in electronics is the term “through-silicon vias” (TSVs). The concept of TSVs is simple: holes are etched through the chip, the holes are plated with metal, and the metal connects to contact points on a second chip lying immediately below the first chip. The process is simple in its explanation, but somewhat difficult to translate into real manufacturing.

Despite a great deal of fanfare, no TSVs were in production as of mid-2008. IBM has announced that the first TSVs would be used in production in the latter half of 2008. IBM’s first application will be in wireless communications chips for the power amplifiers used in wireless LAN and cellular phone applications. IBM is also looking at other applications, including high-end servers and supercomputers.

The excitement over TSVs has been caused by the enhancement in process speed that can be gained by shortening distances. One part of IBM’s announcement says: “The technique shortens the distance information on a chip needs to travel by 1,000 times.” Shortening the lead length by using TSVs reduces the potential for crosstalk between the signal path, the noise on the supply lines, and the earth return paths. The other major source of crosstalk is the multilayering in the chip’s metallization, and this source is unaffected by the introduction of TSVs. Shorter interconnects also reduce power dissipation and improve signaling bandwidth.

Future military systems

The development of future military systems that require extreme levels of processing include integrated systems that bring together, for example, data from missile firings, from night vision systems, from medical body sensors worn by infantrymen, and from other sources. The benefits of command and control that can be derived by using an advanced integrated system based on TSVs are large.

To gain a closer view of TSV technology, we talked with Muhannad Bakir, Deepak Sekar, and Calvin King at the GigaScale Integration (GSI) group at Georgia Tech in Atlanta. Their research is being funded by the Interconnect Focus Center Research Program and the National Science Foundation. The overall purpose of their research can be stated simply: to take advantage of short interconnect distances, they wish to stack high-power chips such as microprocessors, and to run those chips at high frequencies without having them burn out. To do this, they are employing TSVs to create stacks, and are developing a cooling system that will enable the cooling of the stack of hot-running microprocessors.

Currently, high-end processors are often packaged as flip chips. To achieve adequate cooling for one flip chip, a metal heat sink is often adhesively bonded to a heat spreader that is attached to the unpatterned upward side of the silicon die. Creating high-quality thermal bonds between the heat sink, the heat spreader, and the die is a tricky process. If the adhesive is too thick, it acts as an insulator and the chip will overheat. If the adhesive is too thin, delaminations form, the delaminations act as insulators, and the chip overheats. There may be a fan to blow air at the assembly to enhance heat removal as in the case for high-performance chips. Because the metal heat sink lies on top of the chip and has considerable mass and volume, it is essentially impossible to stack such chips. Moreover, because of the large thermal resistance between the die and ambient in such a cooling approach, it is hard enough to cool one high-performance chip. Stacking several high-performance chips increases the power density to levels not possible to cool in such an approach.

The task of heat removal will become even more critical as transistor technology continues to shrink. The projection of the International Technology Roadmap for Semiconductors is that by 2018 the 18 nanometer technology node will have been attained. Both the performance level and the long-term reliability of these future chips will depend on keeping them cool. They will require heat removal ranging from 151 watts per square-centimeter for cost-performance applications to 198 watts per square-centimeter for high-performance applications. Heat subtraction at these rates is beyond the capability of conventional heat sink technology.

Innovative approach

The group at Georgia Tech has taken an innovative approach: etching through-silicon electrical vias (TSEVs) as well as through-silicon fluidic vias (TSFVs), so that a stack of chips has two types of vertical pathways. On the backside silicon of each chip, they etch horizontal micro-channels that link up with the vertical TSFVs to circulate a fluid coolant. The fluidic vias and micro-channels, along with a sealant layer to cap the micro-channels, sockets for the vertical micro-pipes, and solder bumps for the TSEVs, are all formed at the wafer level. After dicing of the wafer, chips are stacked using a flip-chip bonder with an alignment accuracy of less than 2 microns. The goal is to construct a 3D fluidic network capable of removing more than 200 watts of heat per square-centimeter. To date, they have stacked four test chips. Chips that previously would have been scattered across a board are in intimate contact and separated by ~250 microns.

This approach, Bakir says, “ends up allowing you to have a system that can operate at a much higher performance than when you have things dispersed far apart. There is less power being wasted, and less silicon area being used because you don’t have to do advanced equalization and advanced circuit techniques to compensate for the off-interconnect, which is anything but ideal. We’re using wafer-level batch fabrication for the advancement of electrical and thermal interconnects by developing low-cost, high-density, CMOS-compatible electrical and fluidic 3D interconnect networks in a 3D stack.”

The wafers themselves are between 250 and 300 microns thick, roughly half the thickness of an unthinned wafer, but thicker than the dimensions needed for many other 3D techniques, where the wafers (or individual chips) may be thinned down to 50 microns or even 25 microns. Below the active-circuitry device layer on one side of the wafer are 250 to 300 microns of silicon that don’t do anything. “It’s mechanical support, mainly,” explains Bakir. “What we do is take advantage of that available silicon and etch channels directly in that silicon. So the fluidic channels are just a few tens of microns away from where you have your devices. We really try to get the liquid as close to the active circuitry as possible.”

The electrical vias and the fluidic vias are etched from the back side of the wafer. The electrical vias are plated with copper, although the group can make them using other materials, such as tungsten. The fluidic vias are left empty, and are capped at one end with a socket into which is fitted a short length of polymer micropipe that connects to the next die. The circulating fluid the group uses is deionized water, which, Bakir explains, has excellent thermal properties and which will not cause short circuits. Because the coolant is flowing along only about 30 microns (slightly more than 1 mil) from the heat source, and because micro-channel cooling has a high heat transfer coefficient, the heat-subtraction process is extraordinarily efficient. There is no need to use thermal interface materials in this approach.

Vertical fluidic vias

The vertical fluidic vias and their sockets, as well as the horizontal micro-channels are etched into the backside of each chip. After the micro-channels are etched, they are filled with a sacrificial polymer that is spin-coated onto the wafer. After polishing, a second polymer layer is added. Heating removes the first polymer from the micro-channels and from the vias, and leaves the second polymer as a seal over the open micro-channels.

The two chips are connected by the TSEVs and by the TSFVs, but there are other areas that are not connected. These empty areas could be filled by a polymeric material such as a flip chip underfill, Bakir says, but filling the areas may not be necessary.

TSVs offer a performance advantage. Circuit blocks that communicate with each other the most can be placed on top of each other, and therefore the distance that the signals have to travel becomes shorter. Moreover, the pitch (distance) of signal interconnects can be orders of magnitude smaller and thus, bandwidth density significantly higher.

There is a trade-off between interconnect length reduction and the number of TSVs. Most likely, there is an upper limit on the number of TSVs that can be placed in a chip from cost and performance perspectives. Some modeling on this topic has been made, and the researchers anticipate more work will be done on this trade-off in the future.

The architecture of stacks using TSVs more or less dictates that, for maximum enhancement, planning must begin at the chip level so that circuitry is laid out in the most advantageous pattern among the chips, with the most frequently communicating circuits as close to each other as possible. The approach would be unlikely to work, or to work with the greatest processing speed, if 3D integration via TSVs were an afterthought or if an assembler attempted to stack chips from different manufacturers.

TSV technology

Although TSV technology is still at the research level, Bakir does not think its use in production is far off. “I think the issue of manufacturing–of how you do TSV–is pretty well addressed now. I think TSV technology is fairly mature fabrication-wise. It’s not ubiquitous in the consumer market or anywhere else now, but people have done a fair bit of work on it to know its reliability characteristics, though it will be a bit longer before we have a complete understanding of cost and reliability.”

An obvious application for 3D technology is UAVs, which are process-intensive because of the huge amounts of data they receive, process, and transmit. At the same time, UAVs can benefit greatly from reductions in weight, physical volume, and power requirements that would come with stacking.

Larger enterprises such as the U.S. Army Future Combat Systems are facing the same problem: as processing demands increase from teraflops to petaflops, the space, power, and heat become unmanageable. Armaments can be controlled and directed from the other side of the world. Data from all active areas need to be coordinated via an encrypted satellite communication system. The data may flow in from individual night-vision systems, helmet cameras, helicopter and UAV cameras, text reports, and other sources. A system like this will likely require 10 petaflops of processing power–capacity roughly equivalent to the processing power of 10,000 personal computers–by 2012.

Georgia Tech’s approach may also be useful in mil-aero applications where the processing demands are somewhat less severe, but where savings in power and size matter. For non-high-performance applications, “TSV technology would make sense in places where you have small die,” Bakir says, “because when you have small die that means you can squeeze more out of a wafer so you can sort of justify the cost of the TSV technology. The TSV does add cost to the product; in order for that cost to be offset, you need to get a lot of gains in terms of performance, etc. You also need to offset the costs by having a lot of functional chips come out of that wafer that has the TSVs.”

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