Advanced digital post-processing techniques enhance A-D performance

Jan. 1, 2004
Digital signal processing (DSP) techniques can offer a platform for advances in high-speed analog-to-digital (A-D) converter performance.

Digital signal processing (DSP) techniques can offer a platform for advances in high-speed analog-to-digital (A-D) converter performance. Military system designs such as those found in synthetic aperture radar and digital beam-forming communications systems have pushed A-Ds to their limits. These systems demand more innovative techniques to address their growing performance needs.

A common DSP-enabled technique involves using oversampling in some A-D systems to improve their signal-to-noise ratio. Oversampling in an A-D creates the opportunity to use a digital filter to remove noise from unused frequency bands, which effectively reduces undesired noise and spurious content. In fact, a system can achieve a 6-decibel signal-to-nose ratio improvement when the sampling rate is four times the finite-impulse-response (FIR) filter's bandwidth.

In addition to making incremental performance enhancements, digital post-processing technologies have also provided major architectural improvements in how designers use A-Ds in systems. A great example of this level of improvement can be found in the emergence of receive/transmit signal-processing (RSP/TSP) technologies. The ability to use one high-speed A-D for four separate code-division multiple-access (CDMA) channels has been designed into digital receivers such as the AD6635 from Analog Devices. These types of products provide communication-specific DSP functions that are cost-effective and simple to implement.

Time interleaving

One of the latest opportunities for performance enhancement is in time-interleaving A-D systems. Time interleaving is a mature concept that has enabled the development of advanced test equipment such as 8-bit, 20-gigasamples-per-second digital oscilloscopes.

Even though time-interleaving A-D systems have been in use for more than two decades, tight channel-matching requirements have limited their ability to fulfill wideband 12- and 14-bit applications. Fortunately, recent advances in digital post-processing technologies have emerged to meet this growing need.

Time interleaving of A-D systems multiplies the sample rate by employing m number of A-Ds that sample at 1/m the sample rate of the overall system. Each channel clocks at a phase that enables the system as a whole to sample at equally spaced increments of time, which creates the seamless image of one A-D converter sampling at full speed. Each A-D runs at one-fourth of the overall sample rate. The output happens when all of the individual data outputs interleave in the proper sequence — such as 1, 2, 3, 4, 1, 2, etc.

The obvious benefit of this concept in a synthetic aperture radar system would be the increase in the Nyquist zone (available bandwidth) of the digitizer (A-D); the range resolution would improve according to the following relationship. Channel-to-channel matching has a direct influence on the dynamic-range performance of a time-interleaved A-D system. Mismatches between the A-D channels result in dynamic-range degradation that — in a fast Fourier transform (FFT) plot — show up as spurious frequency components called image spurs and offset spurs.

The image spur associated with time-interleaved A-D systems is a direct result of gain and phase mismatches between the A-D channels. The gain and phase errors produce error functions that are orthogonal to one another and contribute to the image-spur energy at the same frequency location.

Offset differences between the A-D channels generate the offset spur. Unlike the image spurs, the offset spurs do not depend on the input signal. For a given offset mismatch, the offset spurs will always be at the same level. These spurs have a direct impact on spurious-free dynamic range (SFDR), and will thus degrade any receiver's sensitivity.

Extensive studies have produced several mathematical formulas that characterize the relationship between image spur level and channel matching. A simplified "error voltage" approach can help provide a simple method for understanding these relationships. The error voltage is the difference between the expected sample voltage and the actual sample voltage. These differences are a result of a large subset of errors that fall into three basic categories: gain, phase, and offset mismatches.

In a two-converter interleaved system, the error voltages that the gain and phase mismatches generate result in an image-spur Nyquist minus the analog input frequency. The offset mismatch generates an error voltage that results in an offset spur at Nyquist. Since the offset spur is at the edge of the Nyquist band, designers of two-channel systems can usually plan their system frequency around it and focus their efforts on gain and phase matching.

In a four-converter system, there are three image spurs and two offset spurs. The image spurs that gain and phase-mismatches between the A-D channels generate are Nyquist minus the analog input frequency, as well as one-half Nyquist plus and minus the analog input frequency. The offset spurs are Nyquist and at one-half of Nyquist — or the middle of the band.

The gain and phase errors generate error functions that are orthogonal, resulting in a "root-sum-square" combination. An error budget can be developed to determine what level of matching is necessary to maintain a given dynamic-range requirement.

A traditional, two-channel time-interleaving A-D system employs a basic configuration. Channel matching comes through reducing the physical and electrical differences between the channels.

Common reference voltages and carefully matched physical layouts can control gain matching. Manually tuning the electrical length of the clock (or analog input) paths or special trimming techniques that control an electrical characteristic of the clock distribution circuit (rise/fall times, bias levels, trigger level, etc.) can achieve phase matching. The offset matching is largely dependent on the performance of the individual A-Ds.

Common reference voltages and carefully matched physical layouts can control gain matching. Phase matching can be achieved by manually tuning the electrical length of the clock (or analog input) paths and/or through special trimming techniques that control an electrical characteristic of the clock distribution circuit (rise/fall times, bias levels, trigger level, etc.). The offset matching is largely dependent on the performance of the individual A-Ds.

While some of these matching methods are noninvasive, many of them require additional circuitry, which adds complexity and risk. The primary challenge with adding circuitry is the resulting error behaviors, such as trim resistor temperature coefficients, and bias current changes over life.

Performance breakthroughs

The development of new DSP techniques, along with the advances in inexpensive, high-speed, configurable digital hardware platforms, has opened the way for breakthroughs in time-interleaving A-D performance. Digital post-processing approaches have several advantages over more traditional analog matching techniques. They are flexible in their implementation and can be designed for precision well beyond the A-D resolutions of interest.

This concept employs a set of digital calibration-transfer functions that separately process each A-D's output data, creating a new set of "calibrated outputs." These digital-calibration transfer functions can be implemented using a variety of digital filter configurations.

Wide bandwidth and temperature matching presents the greatest opportunity — and challenge-for using digital post — processing techniques to improve time-interleaving A-D performance.

The mathematical derivations required for designing the digital calibration transfer functions for multiple A-D channels over wide bandwidths and temperature ranges are complex and not readily available. A great deal of academic work has been invested in this area, creating several interesting solutions — one of which, known as Advanced Filter Bank (AFB), stands out in its ability to provide a platform for a significant breakthrough.

AFB is one of the first commercially available digital post-processing technologies to make a significant impact on the performance of time-interleaving A-D systems. By providing precise channel-to-channel gain, phase, and offset matching over wide bandwidths and temperature ranges, AFB effectively attenuates the image spur and positions itself to establish 12- and 14-bit time-interleaving A-D systems. In addition to this breakthrough benefit, AFB also provides phase linearization and gain-flatness compensation for A-D systems.

By using a unique multi-rate FIR filter structure, designers can implement AFB easily into a convenient digital hardware platform, such as a field-programmable gate array (FPGA) or a complex programmable logic device. The FIR coefficients are calculated using a patented method that involves a variety of advanced mathematical techniques.

AFB enables time-interleaving A-D systems to use up to 90 percent of their Nyquist band, and can be configured to operate in any Nyquist zone of the converter. The appropriate Nyquist zone can be selected using a set of logic inputs, which controls the required FIR coefficients.

A two-converter system that has implemented AFB, for example, features a front-end circuit that provides 400 MHz of bandwidth, a very low jitter clock distribution circuit, two 12-bit, 200-megasample-per-second A-D channels, and an AFB implementation using an FPGA. Many of the traditional matching techniques helped allow proper comparison studies. These key components combine to develop a 12-bit, 400-megasample-per-second A-D module that performs well over 90 percent of the Nyquist band and 70-degrees-Celsius temperature range.

The transfer functions of the A-Ds are characterized using wide-bandwidth- and wide-temperature-range measurements during the manufacturing process. This routine feeds the measured transfer functions of the A-Ds directly into the AFB coefficient calculation process. Once FIR coefficients are calculated for each calibration temperature, they are loaded into the FPGA and the module is ready for action. The FPGA program facilitates the wide-temperature performance by selecting the correct FIR coefficient set.

The dynamic range degrades rapidly as the frequency and/or temperature deviates from the manual trim conditions. This rapid rate of degradation can be anticipated in any two-converter system by analyzing some of sensitive factors associated with this circuit. For example, a typical gain temperature coefficient of a high-performance, 12-bit A-D is 0.02 percent per degree Celsius. In this case, a 10°C change in temperature would cause a 0.2 percent change in gain, resulting in an image spur of 60 decibels referenced to the carrier.

When AFB compensation is enabled, the dynamic-range performance exceeds the 12-bit level (74 decibels referenced to the carrier) across a bandwidth of 180 MHz and a temperature range of 40°C. One final advantage of this approach is its ability to scale for larger bandwidths and temperature ranges as required.

Mark Looney is a design engineer in the multichip products business unit of Analog Devices Inc. of Norwood, Mass. His e-mail address is [email protected].

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