Military researchers ask industry to develop in-memory computing with power efficiency for simulation

March 7, 2023
NaPSAC aims to develop in-memory computing architectures capable of transformative advances in computing accuracy, scalability, and power efficiency.

ARLINGTON, Va. – U.S. military researchers are asking industry to develop ultra-low power in-memory computing architectures for application to scientific modeling, simulation, and analysis.

Officials of the U.S. Defense Advanced Research Projects Agency (DARPA) in Arlington, Va. have issued a broad agency announcement (HR001123S0024) for the NanoWatt Platforms for Sensing, Analysis, and Computation (NaPSAC).

NaPSAC aims to develop in-memory computing architectures capable of transformative advances in computing accuracy, scalability, and power efficiency.

Performers will validate and benchmark compact efficient in-memory computing engines capable of performance beyond conventional von Neumann approaches in scientific modeling of complex, multi-spatiotemporal, and nonlinear problems.

Related: Why test automation is so critical to the aviation sector

Examples of such problems include advanced materials discovery, chemical synthesis, radiation electrodynamics, fluid dynamics, energy or mass transport through heterogeneous media, semiconductor device design and fabrication, and Earth-system models.

In-memory computation runs calculations entirely in computer memory, and implies large-scale, complex calculations that require specialized systems software to run the calculations on computers working together in a cluster.

NaPSAC seeks to develop devices that can demonstrate advanced in-memory computing performance in increased computing accuracy; improved scalability; and enhanced parallelism. Researchers particularly are interested in in-memory computing engines based on nanophotonic or nano-electromechanical (NEMS) resonator arrays.

Proposals should revolve around peripheral architectures that interface with their computing cores to maintain the requisite power budget within a manageable footprint.

Related: Addressing Integrated Modular Avionics architecture challenges with early system-level modeling/simulation

Proposals also may focus primarily on innovations of the computing core if they can demonstrate that peripheral circuitry is compatible with electronic components like digital-to-analog converters, switches, multiplexers, and analog-to-digital converters.

NaPSAC is a four-year program with a two-year first phase and a two-year second phase. The project should begin around November 2023. DARPA researchers say they plan to make several contract awards.

Companies interested should upload proposals no later than 4 April 2023 to the DARPA BAA website at https://baa.darpa.mil.

Email questions or concerns to Mukund Vengalattore, the DARPA NaPSAC program manager, at [email protected]. More information is online at https://sam.gov/opp/11196ccdd2e94c929fb9292e1e62e315/view.

About the Author

John Keller | Editor-in-Chief

John Keller is the Editor-in-Chief, Military & Aerospace Electronics Magazine--provides extensive coverage and analysis of enabling electronics and optoelectronic technologies in military, space and commercial aviation applications. John has been a member of the Military & Aerospace Electronics staff since 1989 and chief editor since 1995.

Voice your opinion!

To join the conversation, and become an exclusive member of Military Aerospace, create an account today!