By John Rhea
Military and aerospace electronic applications still lack a coherently standard approach to microprocessors, despite a long and frustrating history of attempts to settle on just a handful of computer components
It has become an electronics design rule of thumb that microprocessors are the heart of today's military and aerospace systems. Still, the sheer performance of modern chips are progressing so rapidly that they are leaving in the dust the very the systems they are designed to enhance.
The situation represents, in electrical engineering terms, a classical impedance mismatch between the three-to-five-year product life cycles of advanced components and the lengthy development cycles of the intended platforms, which typically run five to ten years, with follow-on support cycles that add another 20 years or more.
This is a downside of today's commercial off-the-shelf (COTS) era, in which the dynamic consumer markets are demanding ever-shorter product life cycles. The major military and aerospace customers simply cannot keep up the pace. Exacerbating the problem further are old and proprietary electronic architectures that constitute barriers to taking advantage of new commercially developed technology.
Illustrating the dilemma of trying to implement state-of-the-art electronics in mature systems is NASA's ordeal in trying to keep the Hubble Space Telescope operational. One case in point involved the Space Shuttle repair mission last December when crew members repaired the faulty gyroscopes on the Hubble. During this mission, astronauts essentially replaced the existing Intel 386 microprocessors that help stabilize the telescope with slightly more powerful Intel 486 chips.
Most people know that the Intel 386 and 486 are rarely seen anymore on any but the most obsolete personal computers. Yet as far as these chips are behind today's leading edge microprocessors, they represent a big advance over the Hubble's proprietary design based on late 1970s technology that NASA originally employed. In fact, the 386 chips were installed during the first Hubble servicing mission in 1993. They were to act as co-processors with the initial computer, an in-house design designated the DF-224, and thus helped NASA officials avoid the expense of upgrading the Hubble's software as well.
The Hubble challenge
The net result is that NASA got six times the memory and twenty times the computer processing speed with the successful replacement of Hubble's onboard computer last year. Yet the improvement could have done much better if the spacecraft design could have accommodated the new Intel Pentium or Motorola PowerPC microprocessors - and if those chips were available in acceptable grades to withstand the radiation and temperature extremes of space.
The problem that NASA faces is not confined to microprocessors and digital signal processors, notes John Hartman, president of Worldwide Business Associates, a consulting firm based in Eaton Center, N.H. Yet NASA officials experience this problem most acutely with microprocessors because these devices are so important to overall system performance. Linear devices usually have similar pinouts - "an op amp is an op amp is an op amp," Hartman points out - but not always. The same mismatches also occur in memory devices.
The solution is to find some kind of open-system architecture that will accept today's devices and still permit designers to drop tomorrow's devices into the same slots as they become available. This is what the now-defunct Joint Integrated Avionics Working Group - better known as JIAWG - attempted to do a decade ago when its officials tried to standardize on the Intel 80960 (I-960) microprocessor. Under JIAWG guidance, designers of the U.S. Air Force Lockheed Martin F-22 Raptor jet fighter and the U.S. Army Boeing/Sikorsky RAH-66 Comanche scout-attack helicopter settled on the I-960 as the central avionics processor on those two aircraft. At that time, the F-22 was known as the Advanced Tactical Fighter, or ATF, and the RAH-66 was known as the Light Helicopter Experimental, or LHX.
Avionics standardization also was the goal of the MIL-STD 1553 data bus and 1750A standard avionics computer architecture, which continue to do so to this day, yet industry opinion has it that general acceptance of these latest standards is nowhere in sight. While the I-960 continues in the U.S. Army's AH-64 Apache helicopter (under a lifetime buy), it is giving way to the Motorola PowerPC family, which one observer called "the processor of choice," in the U.S. Air Force's F-22.
The PowerPC application in the F-22 is in communications subsystems, and the goal is to make these subsystems modular in order to be compatible with the same application in the Army's Comanche helicopter. The Defense Department originally envisioned a tri-service modular avionics program involving the F-22, the Comanche, and the subsequently canceled Navy A-12 attack bomber - then known as the Advanced Tactical Aircraft, or ATA.
Despite well-intentioned efforts, full commonality among the services' avionics needs did not occur. Still, alternate methods at the subsystem level do offer a way out of the dilemma. "Open architecture using the 1553/1750A concept with constant card-level functionality and backplane functionality and a lot of forward design and manufacturing flexibility solves a lot of problems," Hartman comments. "The trick is to keep the obsolete IC component problem at the card level, not at the system level."
Gordon Kranz, chief engineer for tactical avionics systems at General Dynamics Information Systems (GDIS) in Bloomington, Minn., calls this process a "technology roll," which he defines as replacing a current product with a subsequent generation of a product from the same family. The idea is to use a scaleable open-system architecture to continually upgrade several weapon platforms at a time.
During its previous incarnation as Control Data Corp. and later as Computing Devices International, GDIS dominated the U.S. Navy airborne computer market with its AN/AYK-14, of which more than 10,000 systems have been fielded. How-ever, this computer was based on 1970s technology, so in the mid-1980s the company began migrating the AYK-14 product line. The AYK-14 design moved toward an open-system architecture beginning with a radar data processor for the Airborne Warning and Control System (AWACS) aircraft using a MIPS R3000 processor licensed by MIPS Technologies Inc. of Mountain View, Calif., and produced by a variety of component vendors.
As a result, GDIS designers were able to use a commercially designed microprocessor that already had the necessary software development tools available off the shelf. The approach then extended from AWACS to the U.S. Marine Corps Bell/Boeing V-22 Osprey tiltrotor aircraft. The next step, taken in the early 1990s, was to form a joint venture among GDIS, Boeing Co.'s St. Louis operations (formerly McDonnell Douglas), and Honeywell Digital Avionics Systems in Albuquerque, N.M., to extend the open architecture still further to the Marine Corps AV-8B Harrier jump jet, the Air Force's F-15 fighter, the Navy's F/A-18 Hornet fighter-bomber family, and to the T-45 trainer aircraft.
As the program evolved, the GDIS-Boeing-Honeywell team standardized the hardware portion of the architecture as the 6U VME form factor with PowerPC processors and PCI interfaces. The core system software was defined as an object-oriented application programming interface and the application software, which Kranz says he regards as the most expensive portion of the architecture. The core system software is based on industry standard software interfaces such as CORBA and POSIX.
A supplier of microprocessor modules to GDIS for the V-22 program is Aeroflex Circuit Technology of Plainview, N.Y., which has a technology roll of its own underway. The idea is to use the latest MIPS parts in multi-chip modules (MCMs), simply dropping them into the same slots and doubling performance in the process, explains Karl Walter, MCM product line director at Aeroflex.
The company is currently making the transition from the R4400 MIPS chip to the 5271 and has begun shipping the latter part. Aeroflex designers buy the chips from Quantum Effect Devices, a fabless semiconductor house in Sunnyvale, Calif. Aeroflex then packages the new MCM - designated the ACT-5271SC 64-bit superscalar with 2 megabits of embedded secondary cache - in a 280-lead ceramic flat pack. The R4400-based MCM - which was also used in the U.S. Navy Ticonderoga-class (CG-47) Aegis cruiser, the upgrade to the Patriot missile, AWACS, and the AYK-14 - had one megabyte of embedded secondary cache.
"The beauty of the MIPS architecture is that you can stay with the same pipeline structure," Walter comments. Moreover, designers can use the same software, and the devices comply with the MIL-STD 883 ruggedization and traceability guidelines. Despite the improved performance, however, the prices do not change. These are market-driven, he notes, and run between $5,000 and $10,000. Aeroflex officials now are beginning to extend this concept to other avionics applications, including those with a different form factor, such as missiles and cockpit graphics.
There are more than a dozen other suppliers of MIPS devices, including Integrated Devices Technology in San Jose, Calif., Performance Semiconductor Corp. in Sunnyvale, Calif., and such overseas licensees as NEC and Toshiba. Another licensee, LSI Logic of Milpitas, Calif., continues to supply complex application-specific integrated circuits for embedded processors, but is phasing out its military business, says MaryBeth Rottermund, LSI's marketing director.
Lockheed Martin's Space Electronics and Communications operation in Manassas, Va., meanwhile, is building on the microprocessor line that the company inherited with its acquisition of the IBM Federal Systems Division. The Manassas facility was one of the original participants in the Very High Speed Integrated Circuit (VHSIC) program sponsored by the Defense Advanced Research Projects Agency (DARPA), and that technology fed into a family of 16- and 31-bit computers.
The family began with a 16-bit MIL-STD 1750 version, reports Victor Scuderi, business area manager for space processors. In 1992 Lockheed Martin designers began using a 32-bit RISC architecture of commercial design in its RAD 6000. These can be mixed and matched, as they are in the Loral Globalstar telecommunications satellite program, in which each spacecraft uses two 1750 units for command and control and two RAD 6000s for the Global Positioning System (GPS) receiver.
Lockheed Martin has the rights to the PowerPC 750 and produces a radiation-tolerant (200 kilorad total dose) version. However, Scuderi calls the 32-bit RAD 6000 the company's "workhorse" and says he expects to use new packaging techniques, including Compact PCI. Lockheed Martin designers also are proposing members of the /rad 6000 family for the X-2000 program of standardized spacecraft electronics now under way at the Jet Propulsion Laboratory in Pasadena, Calif.
MIL-STD 1750A
Not all 1750As are compatible, but they are scaleable and represent a growth path for the introduction of new technology, notes Richard Comfort, vice president at CPU Technology in Pleasanton, Calif. CPU Tech late last year went into production on an advanced version of that standard computer for the Air Force's F-16 fighter that is projected to be capable of 60 million instructions per second, or MIPS, from a single-chip microprocessor of the company's design. Today's state of the art for the F-16 computer is 1.8 MIPS, as measured by the Digital Avionics Instruction Set (DAIS) system of benchmarks.
Initially operating at only 18 DAIS MIPS, the new 1750 A will go into the F-16's airborne display generator. CPU Tech is the subcontractor to the Honeywell Avionics operation in Albuquerque as part of a major avionics upgrade of the F-16 fleet, which is expected to cost at least $1 billion. The prime contractor is Lockheed Martin Tactical Aircraft Systems in Fort Worth, Texas, under a program known as the common configuration implementation program. More than 1,000 aircraft eventually may be part of the upgrade, including F-16s produced in Europe.
In contrast to the existing 1750A on the F-16, CPU Tech's CPU1750A-60 is truly a "system on a chip," Comfort says. The existing 1750A is a 16-bit processor on three boards with a two-chip set from Performance Semiconductor and has 1 megabyte of memory. The CPU Tech CPU1750A-60 operates either as a 16 or 32 bit architecture with a one-chip set and 4 megabytes of memory (expandable to 8 gigabytes) on one board. The company's strategy is to own the intellectual property rights to the design and farm out fabrication of the chips to commercial foundries, he adds.
This foundry-independent approach proved beneficial when National Semiconductor Corp. of Santa Clara, Calif. exited the digital business to concentrate on its traditional analog products after the design phase of the upgrade had begun. CPU Tech switched to Epson America and delivered its first chips last fall.
The key to scaling up a system without software changes or other disruptions is focusing the effort on the intellectual property rights, Comfort says. "Software doesn't change," he notes. "You may want to stick new software on top of what you have." Nor does the hardware configuration. "The reality is that no particular instruction set architecture is better than any other."
The common thread running through all these efforts to take advantage of the latest model microprocessors is the lack of a one-size-fits-all solution.
It is unlikely that the manufacturers of commercial microprocessors will extend their life cycles or even devote much effort to servicing the modest military and aerospace market, so the specialized suppliers to this market are on their own in implementing COTS. They can begin by following Hartman's advice not to disrupt the systems and Comfort's advice to hang on to the intellectual property rights.
Rad-hard microprocessor technology applied to satellite power systems
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PALM BAY, Fla. - Intersil Corp., a producer of radiation-hardened microprocessors, is applying ruggedized microprocessor technologies in a new emphasis on radiation-hardened devices for satellite power conditioning and power switching.
The company, which qualified for screening to the new Class T flow, is producing a family of metal oxide semiconductor field effect drivers, bridge drivers, comparators, regulators, and references.
Intersil previously pioneered radiation-hardened (to 100 kilorads total dose) microprocessors based on the Intel 8086 architecture, including the 286 and 386. A new 16-bit controller, rated to 300 kilorads total dose, employs reduced instruction set architecture.
The purpose of the power components, according to Jerry Kim, space and defense power marketing manager, is to increase the level of integration from discrete devices to a single package in satellite power systems, which cannot tolerate power interruptions.
The devices are sold through commercial channels, including authorized distributors. - J.R.
SOI microcontrollers used in high-temperature engine tests
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PLYMOUTH, Minn. - A companion technology to military-grade microprocessors is the high-temperature controllers used originally in down-hole oil instrumentation and now being considered for use in aircraft controls.
One of the participants, the Honeywell Solid State Electronics Center in Plymouth, Minn., is using silicon-on-insulation (SOI) technology in new multi-chip modules for distributed engine control.
The company successfully demonstrated operation at temperatures of 225 degrees Celsius at a Pratt & Whitney jet engine test facility in West Palm Beach, Fla., as engine speeds were varied from idle to full-military-power levels.
The components are manufactured using the SOI process at near- and submicron feature sizes, and include a bus interface controller and 8-bit microcontroller. The company claims more than 2 million device hours of life test data at the higher temperature ranges.
This is an example of applying commercially generated technologies to military applications, and the Honeywell center did preparatory work for the U.S. Air Force Wright Laboratory in Dayton, Ohio, under that organization's High Temperature Electronics Consortium program. - J.R.
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