Competition heats up to upgrade 1750A processor

Nov. 1, 1998
WASHINGTON - A competition will decide how to upgrade and extend the useful life of the U.S. Air Force`s 1750A airborne computer, of which upwards of a million have been built since its origins in the early 1970s.

By John Rhea

WASHINGTON - A competition will decide how to upgrade and extend the useful life of the U.S. Air Force`s 1750A airborne computer, of which upwards of a million have been built since its origins in the early 1970s.

The choices have narrowed to a software emulation on a commercial off-the-shelf (COTS) microprocessor and a custom applications-specific integrated circuit (ASIC).

Taking the software-emulation approach is TRW Avionics Systems Division in Dayton, Ohio, under a program known as Reconfigurable Processor for Legacy Avionics Code Execution (RePLACE).

This program received an initial $3.3 million last year from the Air Force Research Laboratory (AFRL) at Wright-Patterson Air Force Base, Ohio, for a technology demonstration using the fire control computer of the F-16 aircraft.

Laboratory testing was completed at the Air Force`s Avionics Lab in Dayton in September, and flight tests are scheduled for next May under a $1.2 million add-on contract.

Offering a competing approach is CPU Technology Inc. of Pleasanton, Calif., which has designed an ASIC to do the same job in hardware. CPU is working under a contract from Honeywell Defense Avionics Systems in Albuquerque, N.M. The purpose is to upgrade the F-16`s color programmable display generator as part of the Air Force`s Common Configuration Implementation Program (CCIP).

The significance of these efforts extends far beyond the F-16 - and, for that matter, the 1750A - because there are at least a thousand aircraft in the CCIP, including the B-2 bomber and the new F-22 fighter. Also, there are other legacy airborne processors, such as the AN/AYK-14 and Z-8000 series, that are in need of upgrading.

John Luke, manager of AFRL`s Reconfigurable Aerospace Computer Emulator (RACE) project at the Information Directorate at Wright Patterson Air Force Base, Ohio, spelled out the program in a presentation at this year`s National Aerospace Electronics Conference (NAECON) in Dayton in July.

He says the problem is being able to introduce new COTS microprocessors while avoiding the considerable expense of rewriting all the software. The expanding missions envisioned for the aircraft demand more embedded software to run operational flight programs (OFPs). He estimates the emulation approach will save the Air Force billions of dollars.

TRW and AFRL have developed the emulator in hardware using a PACE 1750A chip with a Motorola single-board processor in a VME chassis that can run old binary code. It also adds functions written in Ada or C++.

Luke maintains he can extend the same technology to the Z-8002 and to the U.S. Navy` s AYK-14. TRW initially achieved 4 million instructions per second (MIPS) execution time with a 133 MHz Radstone PowerPC 603e processor, as based on the Szewerenko benchmark.

Using the same benchmark, company engineers have since achieved 6 MIPS with a 200 MHz Power PC 603e and 8.8 MIPS on a 233 MHz PowerPC-750. However, RePLACE technology is applicable to other microprocessors, Luke says.

William Cannon, manager of legacy processor technologies at TRW in Dayton, says the militarized COTS boxes will run $60,000 to $150,000 apiece depending on the I/O and processors and that typical non-recurring engineering per system will run $1 million to $2 million.

The company licenses the software and provides the support tools for the new hardware- software environment. Most OFPs require at least 20,000 lines of code, Cannon says, adding that the emulator can handle either the old MIL-STD 1553 or the new Fibre Channel databuses.

Richard Comfort, marketing manager at CPU Technology, says his ASIC can do the same job without replacing any of the software. Fabbing the CPU ASIC is National Semiconductor, Santa Clara, Calif.

In the case of the Honeywell job, CPU delivers the chips, about one inch on a side, which are then mounted on a board of the 1750A. He uses the Digital Avionics Information System benchmark and claims throughput for the ASIC-implemented 1750A is 11.6 MIPS with a peak speed of 60 MIPS for the specialized Honeywell application.

On one point everyone agrees: try to avoid rewriting software if at all possible.

Comfort estimates a line of military avionics software can cost as much as $1,000 to rewrite. On top of that is the cost - and lengthy time delays - of flight testing to reassure the users that the solution is workable.

There is also universal agreement that the 1750A must be upgraded, particularly if it has to be used extensively in the B-2, F-22, and perhaps the Joint Strike Fighter.

Voice your opinion!

To join the conversation, and become an exclusive member of Military Aerospace, create an account today!