Sanders uses clockless logic to improve the efficiency of signal
By John Haystead
NASHUA, N.H. - Engineers from two companies that specialize in digital signal processing (DSP) applications are trying to get out from under the limitations that system clocks impose so they can improve the performance of military and aerospace electronics gear.
While Boolean logic is part of nearly every computer-based system, it can only describe the data processing aspect of a circuit, not address the circuit`s I/O functions. Boolean logic cannot sense when data processing is complete or when the circuit is ready for new data. A clock must control input and output, so systems developers must accommodate circuit delays during the design process.
To overcome these problems, engineers from Sanders, a Lockheed Martin Company in Nashua, N.H., and from Theseus Logic in Minneapolis, are applying clockless logic technology to DSP applications to improve the efficiency of military signals intelligence and information-gathering systems.
Working under a three-year, $1.6 million research contract from the U.S. Defense Advanced Research Project Agency (DARPA) in Arlington, Va., Sanders and Theseus specialists are designing and developing integrated circuits using Null Convention Logic (NCL), an asynchronous digital circuit design method.
Clockless logic circuits reduce a chip`s processing time by avoiding the time-dependency limitations inherent in traditional design approaches. They also reduce power requirements, improve IC reliability, and allow developers to design ICs more rapidly than they can with conventional methods.
With funding from DARPA`s Information Technology Office, the contract calls for Sanders and Theseus engineers to integrate clockless circuits into real-time tactical equipment such as wideband electronic warfare, data acquisition, and electronic intelligence systems. Administering the project are officials of the Army Intelligence Center at Fort Huachuca, Ariz.
"Clockless logic systems will provide signal identification from `voice to microwave` frequencies at accelerated speeds that are solely dependent upon the material composition of the processing circuit," says Ken Stevenson, the Sanders clockless logic program manager, as well program manager for advanced receivers and transmitters. "Clockless logic will also achieve reduced power consumption when compared with equivalent clocked logic circuits due to their inherent power adaptability."
Clockless logic
Clock design, distribution, and management required with Boolean logic is a critical issue within the semiconductor industry. Clocks account for as much as 50 percent of the design cost, as much as 25 percent of the manufacturing cost, and as much as 40 percent of the power use.
More importantly, clocks present a potentially intractable barrier to using increasingly dense fabrication technologies. As transistor feature sizes decrease, designing and distributing clock signals becomes increasingly difficult.
"To overcome these issues, NCL uses a clockless logic technology that represents a major change in designing asynchronous digital circuits and systems," says Karl Fant, CEO and founder of Theseus Logic. "NCL has no time relationships and is insensitive to the propagation delays among component elements at the logic level. NCL promises to eliminate all clocking effects, their circuits and transmission lines, and reduce power consumption", he says.
As a result, NCL has the potential to revolutionize the way engineers design digital circuits, and has many applications in DSP and embedded computing systems. Since NCL is compatible with conventional logic, there is no need to redesign entire systems, only those that present bottlenecks in existing systems.
The Theseus NCL enables engineers to design asynchronous circuits without any detailed timing analysis, and eliminate clock design and distribution problems. To accomplish this, designers must implement null logic gates as discrete threshold gates.
System benefits
Using NCL, designers can integrate system components designed by different groups using different technologies. The various chips will automatically adapt to the different inherent operational speeds among themselves, and account for interconnect delays between chips.
If one chip requests data from another, the first will wait until it has received the data from the second before it continues processing. The entire collection of chips will operate as a delay-insensitive system with no timing requirements or clock deadlines.
To demonstrate this, Theseus has built an NCL asynchronous butterfly function on a Xilinx 4010 field-programmable gate array (FPGA). The butterfly, which consists of an adder, subtractor, and multiplier, is the major building block of the Discrete Cosine Transform (DCT) circuit.
The prototyping capabilities of the FPGA verified the DCT design prior to fabrication of a custom 0.8 micron complementary metal oxide semiconductor application-specific integrated circuit (ASIC). "Because of the delay insensitivity property of NCL, verification using the Xilinx FPGA automatically implies full verification of the custom ASIC implementation. It was not necessary to do any timing analysis at all," says Theseus Logic`s Fant.
Rapid prototyping
Using the 4000 series of FPGAs from Xilinx, Theseus engineers have developed a rapid-prototyping environment for NCL circuits. The Xilinx 4000 FPGA consists of a row/column array of individual look-up tables. The contents of these tables and their interconnections, are all programmable.
"In these devices, NCL asynchronous circuits are implemented as threshold functions with hysteresis", Fant explains. Designers implement the threshold function by initializing a look-up table with a specific set of values. "Hysteresis is achieved through a feedback connection from the output of a look-up table to one of its inputs," he adds. "This method provides a direct mapping of NCL circuit designs onto the Xilinx chips, without the need for any type of logic conversion or emulation."
Once developers download a design into the FPGA, they test it using pattern generators and logic analyzers. The look-up table implementation of threshold gates is not as efficient as one using custom circuits, so an FPGA implementation will operate more slowly than an ASIC. Yet the delay-insensitive nature of NCL means that test verification of an FPGA implementation guarantees the correctness of a custom ASIC implementation of the same design.
"This is analogous to wind tunnel testing of aircraft designs, where the test results on small-scale models apply directly to full-scale implementations," Fant explains. "In our case, testing of an FPGA that is operating at its lower speed of operation is enough to verify the correct, high-speed operation of any custom ASIC implementation of the same design."
DSP building blocks
The first important DSP that Theseus engineers designed and tested is now undergoing testing at Sanders. For the DARPA project, Sanders and Theseus experts are developing the DSP building blocks of a poly phase filter - the key element of a digital receiver that uses data from an analog-to-digital converter to describe an input waveform.
The program complements the Sanders digital receiver testbed and will help establish fabrication costs and schedule for possible insertion into the Lockheed Martin F-22 advanced tactical jet fighter program. Insertion into other programs, such as the future Joint Strike Fighter and Milstar satellite communications program is also possible. "There are a great number of potential applications for the technology with selection based only the limited number of resources we have right now," Stevenson says.
The NCL demultiplexer design and fabrication is already complete, and Theseus designers have received the 16-bit adder and 8-bit multiplier which are the building blocks for the Finite Impulse Response (FIR) filter which is the next major DSP they will build.
Experts are fabricating the devices at foundries using the Hewlett-Packard MOSIS (0.5 micron) process. Fabricators have demonstrated 100 percent yield on the chips and have met their throughput-time design goals of 200 MHz with a 35% margin (70 MHz) at 3.3 volts, Stevenson says.. "At 1.5 volts there is a twenty-to-one power-consumption reduction with less than a four-to-one reduction in throughput speed," Stevenson says.
"Using NCL, no additional margins need be added to worst-case propagation times for setup, hold, and clock skew, as with CBL, Fant explains. "This eliminates all failure modes due to timing. Power savings are also realized by the elimination of clocks. Better still, a reduction in the power supply voltage greatly reduces the power consumed by the circuit and increases the processing speed. This contributes to a system with power management without the danger of timing violations", says Fant.
