By John Keller
BOSTON - BittWare Inc. in Concord, N.H., will offer a new family of rugged hybrid signal processing boards based around the Altera Stratix II GX field programmable gate array (FPGA), company officials announced in March at the Military Technologies Conference (MTC) in Boston.
The new processing board features an Altera Stratix II GX FPGA, a processing cluster of four ADSP-TS201S TigerSHARC digital signal processors (DSPs) from Analog Devices, and as much as 1 gigabyte of DDR2 SDRAM memory.
“The debate over FPGAs vs. DSPs in rugged applications is a moot point,” says BittWare President and CEO Jeffrey Milrod. “Military customers today require multi-processor based designs using a combination of floating point DSPs with FPGAs to provide flexibility.”
The conduction-cooled board is optimized for high-end, multiprocessing applications while also enabling flexibility for future adaptability via the Altera FPGA. The Military Technologies Conference was sponsored by Military & Aerospace Electronics magazine.
Much of the board’s power comes from FPGAs. “BittWare’s ruggedized roadmap based on Altera’s Stratix II GX and ECOTS solution [enhanced commercial-off-the shelf] will provide the military and aerospace communities with a COTS solution for the most demanding applications,” says Jeff Lamparter, marketing director of the military and defense business unit at Altera.
The GT3U uses BittWare’s ATLANTiS architecture to interface between the FPGA and DSPs. Implemented in the FPGA, ATLANTiS provides a single solution for the three dilemmas facing multi-processor designs: how to allocate the I/O bandwidth among the processors, how to easily connect the various I/Os to any and all processing resources, and how to integrate FPGA and DSP processing, BittWare officials say.
A processing cluster consisting of four ADSP-TS201 DSPs provides 14.4 gigaflops of floating-point and 57.5 billion operations per second of 16-bit fixed-point processing power per board. The Altera Stratix II GX FPGA provides pre-, post-, or co-processing to complement the DSP processing cluster, while also enabling seamless routing of the TigerSHARC I/O, and simultaneous on-board and off-board data transfers at a rate of over 2 gigabit per second via the ATLANTiS architecture.
The front panel supplies four channels of high-speed SerDes transceivers which can be configured in ATLANTiS to support a variety of I/O protocols including: Aurora, SerialLite, Serial Rapid I/O, and PCI Express. The back panel supplies 10/100 Ethernet, two standard interfaces of either RS232 or RS422, and 34 LVDS signal pairs composed of 16 inputs and 20 outputs.
A BittWare SharcFINe PCI-DSP bridge chip provides the interface between the processing cluster and the DSPs, giving them low-overhead access to the host via the 32-bit, 66 MHz PCI interface. The chip also provides a general-purpose peripheral bus that allows the DSPs to access the 10/100 Ethernet on the back panel, the flash, and the FPGA control registers. Conversely, the SharcFINe provides host access to the DSPs, on-board SDRAM, flash, and FPGA control registers.
BittWare offers software support, including interface libraries and a wide variety of diagnostic utilities and configuration tools. Also available are BittWare’s TS-Lib optimized libraries for TigerSHARC, and board support package (BSP) for Gedae.
For more information contact BittWare online at www.bittware.com.