Actel Corp. in Mountain View, Calif., is offering new capabilities with its Libero 6.3 integrated-design-environment (IDE) software. The Libero 6.3 provides a secure design flow- from synthesis through implementation-for integrating Actel’s CoreMP7 soft ARM7 processor into Actel’s single-chip, nonvolatile field-programmable gate arrays (FPGAs). The software also automates I/O voltage assignment and supports Actel’s RTAX4000S devices. Libero 6.3 provides a block-level methodology that enables designers to aggregate IP around CoreMP7, map it into Actel’s ProASIC3/E FPGA fabric with predictable timing, and verify operation. Tight integration with third-party tools from Magma Design Automation, Mentor Graphics, and Synplicity enables seamless synthesis, verification, and physical synthesis for designs incorporating CoreMP7. For more information contact Actel online at www.actel.com.