Intellectual property offers new choices for avionics design engineers as MIL-STD-1553 and FPGA technologies converge

June 1, 2003
For decades, aerospace engineers have squeezed more and more technology into military airframes. Driven by market requirements nearly as much as by combat necessity, avionics have evolved from simple stand-alone systems to microprocessors necessary to control sophisticated fighter aircraft.

By John Gerngross

For decades, aerospace engineers have squeezed more and more technology into military airframes. Driven by market requirements nearly as much as by combat necessity, avionics have evolved from simple stand-alone systems to microprocessors necessary to control sophisticated fighter aircraft. A significant part of this ever-changing technology has been the advent of the MIL-STD-1553 databus.

Prior to 1970, avionics were simple black boxes that controlled navigation, communications, and flight controls, which were connected with point-to-point wiring. With the introduction of digital technology, computational capability and easy growth increased dramatically. Because analog data signals remained relatively slow, though, systems designers used small, centralized computers as a temporary stopgap that acted as interfaces between systems via complex analog-to-digital and digital-to-analog converters.

Microprocessors reduced the number of analog signals and the need to convert them. What was still necessary, however, was a data transmission medium that would allow all systems to share one common set of wires to send data between systems one at a time in a defined sequence.

Experts from the Society of Automotive Engineers (SAE) began looking at defining a serial databus in 1968. After three years of military and government reviews, the MIL-STD-1553 was released in April 1973, and deployed in the U.S. Air Force's F-16 jet fighter, as well as in the U.S. Army's AH-64A Apache attack helicopter. After three more years of fine-tuning, which produced 1553B, component manufacturers began developing products with a goal of giving the aerospace industry time to gain "real-world" experience before determining what the next set of changes would be — if any.

Avionics designers have seen 1553 test and simulation implementations, like many network technologies, evolve from huge Digital Unibus cards to 19-inch rack-mount boxes to multi-channel standard backplane cards for VME, CompactPCI, PCI, and PCMCIA. 1553 application-specific integrated circuit (ASIC) manufacturers have not been immune to the effects of rapid advances in technology that has resulted in the shrinkage of their implementations from discrete protocol and transceiver chipsets to single, low-profile, and low-power ASICs.

MIL-STD-1553 technology has not advanced so rapidly as its large-market counterparts such as Ethernet, and the old bus is becoming outdated for the most part, except for relatively old applications.

In a bid to meet ever-increasing technical demands, some aerospace companies are looking at the possible convergence of MIL-STD-1553 and Field Programmable Gate Array (FPGA) technology. This convergence eventually may replace the ASIC approach because of its limited functionality and high cost. FPGAs, on the other hand, are generic in nature, fill many roles, are available commercially off the shelf (COTS), and integrate easily on a board.

Initially, FPGAs were simple programmable logic devices (PLDs) that had a handful of logic elements and accomplished basic tasks. Over time, functionality demands grew and technology evolved to allow greater density of logic in these devices. This has enabled the military to cram even more technology into ever-smaller spaces. Also, today's FPGAs offer significantly reduced part counts from electronic architectures of years past. In the past, where you might have had 50 parts, now you may have just one. You've also reduced your mean time between failures (MTBF), resulting in far fewer failures.

When considering an FPGA over a specialized ASIC solution for 1553 applications, the FPGA is a blue-light special by comparison. It's much more flexible, and you can buy FPGAs in all sizes, prices, and performance levels. You can literally pick an FPGA device that meets your particular need, when it comes to size and performance. However, you will incur engineering labor to program the FPGA to deliver the desired 1553 functionality, whereas an ASIC already contains 1553.

Cost, though, is the great equalizer in choosing between ASIC and FPGA. An ASIC that has 1553 functionality in it, might cost you $500. An FPGA that has the same potential as the ASIC, but doesn't have anything in it, might run $80 to $100. You have to ask yourself how are you going to get 1553 in it when you don't want to take many man-years of engineering to come up with those capabilities.

One possible avenue is to use existing technology that will do this for you. Intellectual Properties (IP), are preprogrammed hardware objects that facilitate loading 1553 functionality into an FPGA, resulting in a flexible, 1553-enabled FPGA at a fraction of the cost of an ASIC, especially when large quantities are being installed. FPGA cores represent a breakout from the ASIC mold to IP designs that, in addition to lower costs, can offer better parts management, higher circuit integration, better system performance, and multi-channel, single-chip designs.

Some IP cores require a large amount of FPGA resources, such as on-chip memory and gate counts, and some core implementations, therefore, may not pass a cost tradeoff when a designer can instead choose a high-volume, inexpensive chip. But when it comes to cost versus other considerations, avionics designers usually will opt for space and tightly coupled integration.

The new IP technology provides high-level objects for the electrical engineer, much the same as in the software world where you have long been able to design with libraries of functions that greatly facilitate software development. No longer does a programmer who builds a GUI for Windows have to figure out how to make a pull-down menu. Now they just use conventional, off-the-shelf tools that allow them to concentrate on their jobs of making that GUI do what they want it to. The same conceptual technology is now available to hardware designers who are able to license the piece they need to put their puzzle together. Then all they have to do is meld those pieces together and add their customized function.

The convergence also offers advantages in leveraging off conventional technology. As time goes by, you can increase your ability to grow and evolve the product. You can also leverage off manufacturers by reducing your sole-source limitations. If one FPGA manufacturer fails to perform, you acquire the technology from another. That's competition at its best. And the big issue, as far as the military is concerned, is that it addresses obsolescence.

It's imperative, however, that engineers research suppliers and make sure a vendor's experience level in FPGA designs and testing efforts are sound and well documented. For 1553 core vendors, suppliers need to be able to show that their cores pass the standard 1553 tests.

Reference designs, example programs, and application program interface (API) libraries should be part of any package. A reference card should be an option for testing and debugging. These are usually inexpensive PCI boards that can be an invaluable diagnostic and test resource for the customer and vendor. When the customer can send a modified core object to the supplier to help debug a project, the reference card may be the only common hardware platform for both parties to debug against. Example programs and APIs can often be critical in meeting the design schedule. Even for the best vendors, the documentation does not always explain the implementation as well as a good piece of example code.

There are several reasons for engineers to go with IP designs. Parts obsolescence is one of the major risks for all multi-year electronics production projects. This risk can be greatly reduced with cores because designers are not tied to one specific part, or even one FPGA manufacturer. This is in stark contrast to sole-source, specialized-protocol ASICs and processors (as well as their manufacturing methods), which could be discontinued at any time. With an FPGA implementation for a circuit, the design can be ported to the latest "chip du jour," often without a change in functionality, resulting in fewer software changes, which is often the most expensive part of a project.

Reduced footprint, higher reliability, less power and weight are also important benefits of using IP core technology. Combining several different functions, including processors, I/O, 1553, and backplane circuits into one part will significantly reduce part count, board space and thermal loading. This effectively results in increased reliability (mean time between failure is higher). Reduced part counts can also result in lower system power requirements and save precious weight on aircraft systems.

A third compelling reason of using IP core technology is cost reduction. Production and life-cycle costs will drop with time as a result of implementing FPGA/PLD cores. FPGA/PLD prices have an established history of significantly dropping over time, while small-market ASIC product pricing trends continue upward, or at best, stay constant for long periods of time. A relatively small, portable 1553 core implementation can be dropped into an existing FPGA that is already on the avionics card. So the cost of the FPGA may be free to the core physical cost and the common synthesis and design tools stay common between components.

Finally, soft reconfiguration of the hardware can save valuable engineering resources, time, and cost. Core implementations offer the unique capability that allows the hardware to be reprogrammed in the field. When requirements change or bugs need to be fixed, an FPGA-based design offers tremendous advantages. With 1553 applications, many new computers are being designed to serve several different aircraft platforms. It should be noted that F-16 jet fighters have a different 1553 flavor than F/A-18s, B-2s, B-1s, F-22, or the Space Station. The protocol differences occur at layer-two of the network and a soft, re-programmable 1553 core is ideal for these varied programs.

If you don't have any underlying hardware changes and it's just a protocol change, you're not going to be able to do much if you're working with an ASIC, which is never going to do anything but what it was designed to do from day one. However, if you have an FPGA, with intellectual property design in the mix, you can lay in a new piece of IP that specifically meets the new requirements and, best of all, you most likely will not have to change the rest of the design.

For the original design you might find it's very difficult and expensive, or maybe you can't even accomplish what you set out to do with the ASIC, which you find out the hard way after many months of design. With IP, you have the potential to customize what the lower-level interface is doing. This greatly reduces the risk at the point of initial design, as well as future revisions. IP also offers the potential for customization. With ASIC this will never be possible.

Historically, people would design an FPGA and an ASIC, but now FPGAs can swallow both functions at less cost. Design tools have made it easier to develop hardware that looks more like software, which allows designers to add more functionality in ever decreasing space, as well as the ability to test and validate that functionality.

As FPGAs evolve, it is likely that they will eventually replace ASICs because the military is moving more and more toward COTS equipment and is committed to leveraging off of the commercial industry, which is driven by price/performance. This impetus for the military to follow on the heels of the commercial industry and the FPGA bandwagon is just a natural part of this evolution.

John Gerngross is chief executive officer and founder of Condor Engineering in Santa Barbara, Calif., a supplier of data communications solutions for avionics. His e-mail address is [email protected].

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