A look at the future of stacked die integrated circuits
The terms "stacked die" and "stacked chips" have become very lively buzzwords within the electronics community — so much so that the notoriety of these concepts can obscure the reality.
by Keith Gurnett & Tom Adams
The terms "stacked die" and "stacked chips" have become very lively buzzwords within the electronics community — so much so that the notoriety of these concepts can obscure the reality. Stacked configurations are in production, but there are few, if any, military or aerospace applications to date.
There are plenty of potential applications — signal processing systems such as sonar and radar, wearable electronics such as a wireless unit built into a helmet, and miniaturized sensors for distributed micro-sensor networks. The promise of these configurations is great, and experts are asking how extensive their eventual influence will be in military and aerospace applications.
Stacked-die configurations are much like multichip modules, except that the die are both thinned and placed on top of one another. Thinning reduces overall height, while stacking results in a much smaller footprint and shorter, more substantial interconnections that imply higher speed, less transmission loss, and higher reliability than their multichip module cousins.
By stacking a memory chip on top of an otherwise obsolete ASIC or FPGA, MCE extends the life and enhances the performance of the device.
The narrow, thin traces necessary in the high-density interconnects for multichip modules are inherently more lossy than conventional 1-mil gold wires. Stacked die are still very much like multichip modules, and one of the weaknesses of multichip modules has been the problem of achieving and maintaining reliability in each of the members of the module. There has not yet been sufficient practical experience to know whether stacked die will be more reliable than multichip modules.
Numerous different stacked die configurations are in a late development stage or in early production. One of the most common varieties places a thinned memory device on top of a digital signal processor or other type of processor.
Interconnects between the two die are in most cases via bond wires; innovators in the field of stacked die recognize that there is value in sticking as closely as possible to the use of conventional assembly equipment. Other configurations use two or three chips of decreasing size in a pyramid arrangement, or stack three or more chips of similar sizes. One design problem involves bond wires that must loop upwards from the die and thus add height to the stack. Some innovative stacked-die configurations attempt to solve this problem.
In most current designs, the die that stack on top of the bottom die are memory devices, although the various stacked-chip configurations open up the possibility of using a mixture of semiconductor technologies such as silicon, silicon germanium (SiGe), light-emitting diode (LED), and perhaps micro electro-mechanical systems (MEMS) to provide combinations of speed, logic, and any other function that may be required.
Most of the chip stack variations end up on an interconnect system, invariably of a multilayer format because of the density involved, and terminated in a ball grid array construction on the underside of the interposer, for final assembly.
Cost and reliability
Two of the factors that will determine how widespread stacked die will be in military and aerospace applications are cost and reliability. Dramatically small size and enhanced functionality will not by themselves drive acceptance of stacked die unless costs compare favorably to more conventional designs, and unless designers have reasonable assurance that these designs can deliver long-term reliability.
Lower cost was one of the reasons for the development of 3-dimensional memory stacks at Matrix Semiconductor Inc. in Santa Clara, Calif. Matrix experts made the chips themselves in a conventional CMOS fab, and use conventional materials and production equipment. The small overall size and high yield mean that the overall cost of memory is lower than for traditional DRAM, SRAM, flash, and Mask ROM.
The tendency for developers of stacked die to use conventional wirebonding rather than more expensive flip -hip interconnects is echoed in a recent development from LSI Logic Corp. in Milpitas, Calif. A new packaging approach, developed for LSI's 0.11 micron and 0.90 micron silicon technologies, places wirebonding pads directly on top of active I/Os. Since this design loses no real estate to bond pads, designers can reduce the area of the chip by about 35 percent, and reduce pad pitch by 25 percent. For thinned, stacked die, this cost-sensitive approach means enhanced space savings.
Systems designers at Micro Circuit Engineering (MCE) in Tewkesbury, England, use stacking to solve the problem of upgrading obsolete ASICs and FPGAs. Upgrading of obsolete designs typically involves increased memory requirements, a modification that would traditionally call for an expensive redesign of the chip. MCE mounts a memory die on top of the replacement ASIC or FPGA and adds wirebond interconnections. This permits the use of in-stock replacement chips that would otherwise have to be judged obsolete. It also gives improved performance with no modification of the application-specific integrated circuit (ASIC) or field programmable gate array (FPGA) itself.
Meanwhile, designers at Atmel Corp. of San Jose, Calif., are following a similar route by adding external stacked EEPROM to convert any FPGA or ASIC into an Atmel ULC (Universal Logic Conversion). In its first application, this approach reduced board area for the two devices by 80 percent, and resulted in a package only 1.1 mm in height, company officials say.
Scientists at Infineon Technologies AG in Munich, Germany, developed a process called Solid that is a solid-liquid interdiffusion technique. This makes it possible to redistribute I/Os within the chip surface interconnect system such that two chips can be bonded face to face, and the resulting pair wire bonded to an interconnection package.
This process starts with chips that have been completed with the passivation layer still open. Titanium-tungsten is sputtered onto both wafers followed by a further deposition of a copper seed layer using the sputtering technology. Standard lithography defines the resist function for the insulation trenches. Copper is then deposited onto the seed layer followed by as much as 3 microns of tin-lead solder. Stripping and etching the seed layer along with the exposed titanium-tungsten completes the first stage operation.
The wafer containing the die that goes on top of the two-chip sandwich (the smaller die) is then diced, flipped, and placed on top of its counterpart that is still in the wafer format. Using specially developed bonding equipment the two chips are pressed together and heated to 270 degrees Celsius. Copper reaction with the tin produces an intermetallic phase and continues until all of the tin has reacted and the liquid phase ends. The larger chip carrying the bonded chip can now be diced mounted and bonded by the normal processes.
The interface thickness, compared to the flip-chip solder ball process, results in a thickness interface of only 10 microns compared with 70 to 100 micros in flip chips. The diameter of the interconnecting bonds is only 2 to 3 microns, compared to 100 microns in flip chips. This enables greater density and permits traces under and on top of the oxide, effectively creating another layer of interconnects. Underseal or ring fencing depends on the final packaging solution. This type of stacking avoids any inherent and historic shortcomings of the adhesive approach and at the same time achieves even smaller dimensional restraints.
A very different approach is in progress at Tessera Technologies Inc. in San Jose, Calif., which has introduced its Micro-Z fold-over package technology. The basic idea involves a device such as a digital signal processor placed on a length of flexible polyimide film-base substrate alongside one or more memory devices. The memory chip is initially face down, but reverses its orientation when it is folded over the digital signal processor. The whole package is then encapsulated with a conventional molding compound. Interconnection between the die in the stack is by wire bonds.
Tessera experts claim several advantages for their technology: manufacturing costs should be lowered, the underlying board may require fewer layers, and performance of the digital signal processor (or other processor) may improve. Yield and reliability may be enhanced because the assembly process makes it possible to use only previously tested components, and makes it unnecessary to purchase costly known good die. Tessera officials refer to the process as "mix and match": they can bring components of different types, and perhaps from competing manufacturers, together to create a multichip package with a very small footprint.
The design of Tessera's vertical package addresses the problem of vastly different coefficients of thermal expansion between the substrate and the die by incorporating what company experts call "compliancy" into the package. The die is able to move with respect to the substrate without damage. Nokia has picked out this design as an especially reliable package, in part because of the design's compliancy and in part because its low overall mass makes it less susceptible to the shock and vibration that portable appliances sometimes encounter. Tessera leaders also have extended the idea of this design in their 3- and 4-die folded stacked packages. Meanwhile, Tessera experts also have developed their Micro-Z ball stacked package which uses a multi-die chip-scale package to stack several different memory chips such as DDR-SDRAMs.
It may seem logical that the level of integration that stacking die permits might evolve into single die whose layers of metallization would integrate RF, analog, and digital components. But as spokesmen from Motorola and IMEC in Belgium pointed out at the ISSCC conference in February, such a level of integration, while theoretically possible, would be too expensive for anyone to attempt its development. The concept of stacking die to achieve integration may therefore have considerable longevity.
Many other companies have made some type of advance in stacked die technology. The problems of achieving a smaller footprint and of stacking die by methods that are reasonably inexpensive appear to have been largely solved. Most innovations are careful to make maximum use of existing production equipment, since a stacked die technology requires costly new equipment.