Designers of compute-intensive equipment for military and aerospace applications face many challenges in today's cost conscious and deadline-driven world.

Jan 1st, 2003

FPGAs can meet the challenge of bridging dissimilar interfaces as designers blend old and new data bus architectures

by Ken O'Neill

Designers of compute-intensive equipment for military and aerospace applications face many challenges in today's cost conscious and deadline-driven world. Increasing data-processing requirements in applications such as image processing have highlighted a scalability problem with existing processor-interconnect technologies.

Under pressure to use commercial off-the-shelf (COTS) parts to maintain cost controls and meet tightening project deadlines, designers may find that the ideal components for their designs use one or more new interfaces. A problem arises when devices that must communicate with each other have different interfaces; one example is a MIPS processor with a HyperTransport interface communicating with a memory controller with a PCI interface.

In time, off-the-shelf devices will become available to cover most interface bridging needs, yet that is not the case today. Therefore, it is important to examine some of the limitations of existing interconnect architectures, the alternatives for high-bandwidth interconnect moving forward, and the influence of new interface standards on designers of military and aerospace systems.

Existing bus architectures can provide ample bandwidth for many systems. A few distinct factors limit existing technology architectures — bus architectures, clocking methods, and the move to differential signaling.

Established interface technologies make use of shared multi-drop buses, such as VME and PCI. For high-bandwidth applications — where multiple devices need to send data to each other, the nature of these buses restricts maximum bandwidth. This results in bus contentions because all devices on the bus must share the bandwidth.

Clocking architectures can also limit bandwidth. In complex system with multiple transmitting devices sharing a common multi-drop bus, skew between the clock signal and the data signals can ultimately impose limitations on maximum bandwidth. The problem is even worse in systems where the bus connects devices on multiple boards and where clock and data signals have to travel through connectors and over backplanes.

A change in emerging standards

For those systems requiring large volume data transfers, a new approach is necessary. In lieu of the shared multi-drop buses, today's emerging interface standards use point-to-point connections, such as switch-fabric or tunneling architectures, between devices. The switch-fabric or tunneling devices transmit data in packets, with each packet including source and destination address information useful for routing the data to the correct destination. Separate transmit and receive data paths are provided for each connection.

The shift to switch-fabric or tunneling devices has also been accompanied by a change in clocking methods and architectures. Instead of using a shared system clock, emerging interfaces use individual clocks for each point-to-point link. The clock is forwarded from the transmitting device to the receiving device via source-synchronous clocking or serialization of data signals and an embedded clock. For several of the fastest interface standards, the latter method is chosen. With serial interfaces, there is zero skew between clock and data and multiple lane serial interfaces can achieve bandwidth approaching 10 gigabits per second.

In addition to new architectures and clocking methods, the new generation of interfaces uses differential signaling. Each signal path may be switching at speeds from several hundred megabits per second to several gigabits per second. Traditional single-ended I/O standards are not capable of running at these speeds. In order to keep electrical noise and power dissipation at reasonable levels, differential standards have been introduced, such as low-voltage differential signaling (LVDS) and current-mode logic (CML). With LVDS, signals are indicated the voltage levels on the conductors. With CML, on the other hand, the current levels in the conductors indicate signals.

Standards to watch

Supported by a group of silicon suppliers and system companies through the HyperTransport Consortium, HyperTransport technology is a high-speed point-to-point link for integrated circuits, and is designed to meet the bandwidth needs of tomorrow's computing and communications platforms. The technology helps reduce the number of buses while providing a high-performance link for PCs, workstations and servers, as well as numerous embedded applications and highly scalable multiprocessing systems. Several devices, including MIPS-based processors, are available on the market today using an 8-bit, 500 MHz version of the HyperTransport technology.

Systems designers can use a parallel interface that uses a tunneling architecture, source-synchronous clocking, LVDS electrical signaling, and parallel data widths of 2, 4, 8, 16, or 32 bits in each direction. As a result of these optimizations to the standard's architecture, the clock rate for HyperTransport can be as high as 800 MHz. Further, because signals switch on each edge of the clock, maximum possible bandwidth of 51.2 gigabits per second 6.4 gigabits per second in each direction is possible.

HyperTransport supports auto-negotiation of link configuration at system powerup, allowing devices with dissimilar interface widths and speeds to operate together seamlessly. The auto-negotiation process allows the faster device to configure itself to operate at the speed and width of the slower device.

The PCI-Express technology, a high-speed, scalable serial switch-fabric architecture, has been developed in an effort maximize the existing investment in the installed base of PCI software while avoiding the bottlenecks created by PCI's multi-drop nature. PCI-Express is targeted at the desktop, mobile, server, storage and embedded communications markets. PCI-Express uses CML serial I/Os running at 2.5Gb/s with embedded clocking. Multiple serial lanes can be used to build higher bandwidth connections.

Whereas HyperTransport and PCI-Express have a strong "desktop computing" flavor to their architecture, RapidIO, another switch-fabric interface, has been developed specifically for embedded systems. The parallel version of RapidIO uses LVDS I/Os, configured as 8 bits wide or 16 bits wide in each direction. Data is clocked in a source-synchronous fashion at up to 1.0 GHz, on both edges of the clock for a maximum bandwidth of 32 gigabits per second or 4 gigabits per second in each direction.

Alternately, the serial version uses CML I/Os, configured either as a single lane or as a group of four lanes in each direction. A clock signal is embedded with the data in each lane. The specification provides for clocking at 1.25 gigabits per second, 2.5 gigabits per second, or 3.125 gigabits per second. Since the standard uses 8b/10b encoding, the corresponding data rates are 1.0 gigabits per second, 2.0 gigabits per second, and 2.5 gigabits per second respectively. As with HyperTransport, RapidIO allows for auto-negotiation, enabling the two devices communicating with each other over that link to negotiate the speed of any given link at system initialization.

In another attempt to preserve the substantial investment in driver software over the past decade, the PCI Special Interest Group (PCI SIG) has developed some enhancements to the PCI specification, resulting in PCI-X, the fastest variant of PCI shipping in silicon today. Leveraging a heavily parallel (64-bits wide) multi-drop architecture, PCI-X uses single data rate clocking at 133 MHz in order to provide maximum bandwidth of 8.512 gigabits per second, or 1.064 gigabits per second to be shared between all devices on the bus. The PCI-X technology is frequently deployed as a point-to-point link connecting two devices whereas the 1.064 gigabits per second bandwidth has to support communication in each direction. If each device requests an equal amount of transmit time, then the effective bandwidth will approach 532 megabits per second. The PCI SIG has proposed future versions of PCI-X, which use double-data-rate and quad-data-rate clocking to double and quadruple the bandwidth. These standards are referred to as PCI-X 266 and PCI-X 533.

Implementing emerging standards

Because designers of military and aerospace systems need to have a quick and easy way to bridge dissimilar interfaces, field-programmable gate arrays (FPGAs) represent one of the best alternatives. Today's FPGAs offer sufficient logic capacity and high enough internal performance to allow the integration of emerging interface standards as soft intellectual property (IP). In addition, they support all of the new I/O standards (such as LVDS and CML) that the new interfaces require. An additional benefit is the ability of FPGAs, when used as bridge solutions, can perform some processing on the data as the data passes from one device to another.

When selecting an FPGA to solve an interface interoperability problem, designers must pay careful attention to the capacity of the FPGA, because many of the emerging interfaces are complex and can consume a substantial amount of the FPGA's logic resources. In addition to raw gates, the amount of available memory, the number of clock networks, the operating range of PLLs, the number of I/O's, and the interface standards supported by the I/O's should all be considered.

Frequently, it is insufficient to consider just the logic and I/O demands of the two interfaces to be bridged. Designers also may need to integrate a microprocessor interface, a DSP interface, and/or a memory interface into the FPGA as well. That way, some amount of data processing happens as data passes between the two interfaces. Using the FPGA as a "hardware assist" in this manner can in some cases significantly improve system throughput.

Beyond the fundamental attributes of the FPGAs under evaluation, designers may also wish to consider whether require additional options — guaranteed operation over the extended military temperature range, full MIL-STD-883B screening, and the like. Some, but not all, FPGAs come with this level of screening. It is important to choose an FPGA vendor who understands and is committed to fulfilling the needs of military and aerospace designers.

Power issues

An additional consideration is power consumption. For equipment that is to be portable, or is to operate off a vehicle power supply, power may be one of the critical design factors. Even in situations where supply is not a problem, cooling may be a concern. Systems using emerging interface standards are likely to be high-bandwidth systems, which almost by definition will be running hot. Choosing an FPGA with low power consumption can help with system power supply and cooling problems.

Yet another consideration is security. If the FPGA is used to implement some data processing in addition to interface bridging, it is possible that the FPGA design may represent the key hardware IP in the design. Software algorithms can be copied from the microprocessor code storage space, and standard parts can be purchased on the open market. ASICs can be deprocessed and reverse engineered. Therefore, a secure FPGA represents a safe place to store key design IP and prevent the reverse engineering and design theft that has become so problematic in the commercial world.

Many designers are also seeking ways to re-use existing designs with legacy interfaces, in new systems built around the emerging high-bandwidth standards. In cases such as these is a way to interface the old with the new is required. An FPGA can be an excellent way of doing this, since off-the-shelf FPGAs have support for old and new I/O standards and have sufficient capacity to integrate soft IP for both interfaces.

Ken O'Neill is director of product marketing at with Actel Corp., an FPGA designer in Sunnyvale, Calif.

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