Thermal simulation reduces cost of stacked module potting compound 50 percent

April 1, 2009
C-MAC MicroTechnology, an electronics design and manufacturing company in South Denes, England, developed a stacked module for a defense application.

By Tom Litrenta

C-MAC MicroTechnology, an electronics design and manufacturing company in South Denes, England, developed a stacked module for a defense application. Prior to building prototypes, C-MAC engineers performed thermal simulation on the initial concept design and discovered that junction temperatures on the module ranged up to 125 degrees Celsius, well above the 100 C maximum. They realized they needed a potting compound to reduce thermal resistance and wanted to select the least expensive formulation that would meet the thermal requirements of the application.

“Our engineer simulated the junction temperatures of the devices in the stacked modules while using three different potting compounds,” says Bob Hunt, head of engineering for C-MAC. “He discovered that we could meet the thermal requirements of the application with a potting compound that cost half as much as the highest-performing potting compound. Simulation was much faster and less expensive than the alternative of building and testing prototypes.”

Thermal design challenge

Stacked modules are becoming popular as system complexity and packing density increase. Thermal management is critical in stacked module applications because of power density. The critical task from a thermal standpoint is removing heat from within the stack so it can be dissipated by external heat sinks. The module used in this application incorporates eight packaged devices, one bare die, and two printed circuit boards.

The module is constructed of a ball grid array (BGA) lower circuit board with some of the surface-mount components and an inverted upper circuit board with the remaining devices. The module is partitioned to separate the higher-power components and maintain signal integrity. The interconnect required between top and bottom circuit boards is made via edge connections with support between the two circuit boards provided by a kovar ring frame. The highest-power dissipating component, the S C ASIC, is on the lower circuit board while the next highest, the TSB41BA3, is on the upper circuit board in a diagonally opposite corner. Heat can then be transferred out of either or both the upper or lower surfaces.

Simulation streamlines design process

Jonathan Crossley, C-MAC senior engineer, performed thermal simulation on the initial design using FloTHERM computational fluid dynamics (CFD) software from the Mentor Graphics Mechanical Analysis Division (formerly Flomerics). “It provides many tools that reduce the time required to model complex stacked module designs,” Crossley says. “The most important of these tools is the FloTHERMPACK Web-based wizard, which quickly produces accurate models of integrated circuits and other components.”

Crossley began the modeling process by gathering information on component package styles and power dissipations. Then he used FloTHERM to generate a conceptual model by defining the dimensions and the substrate, underfill, and cavity materials. He constructed the model of discrete cuboids with material properties, most important thermal conductivity, assigned to each.

Crossley used FloTHERMPACK to generate models of each of the components. “It would have taken a considerable amount of time to define the geometry of each of these components to the level required to obtain accurate junction temperature predictions,” Crossley says. He entered into the FloTHERMPACK wizard basic design parameters such as the die size, die flag size, and lead frame clearance. “FloTHERMPACK generated models of the components that were almost there. I had to make minor modifications and they were ready to insert in the model. I was able to model this stacked module with FloTHERMPACK in less than half the time that would have been required using conventional modeling methods.”

Next Crossley defined the size of the cells in the model, using smaller grid cells in areas where more detail was needed. He also defined the environment in which the module is mounted in the end application. At this early stage in the design process, it was necessary to make some assumptions, included mounting the module on an infinite heat sink with the temperature held at 70 C.

“The simulation results for the initial concept design showed that junction temperatures were much too high, up to 125 C,” Crossley says. “The next step was to try a potting compound to reduce the thermal resistance of the module and conduct heat from the devices more readily to the heat sink. Our goal was to find the least expensive potting compound that would maintain junction temperatures of all devices on the board safely within the design spec.”

The optimal thermal solution

“The traditional method to address this goal would have been to build prototypes and run physical experiments with each type of potting compound,” Crossley says. “But it would have taken a considerable amount of time and money to build prototypes, assemble them with different types of potting compounds and run physical tests. The hardest part would have been measuring the junction temperature of the different devices.”

Crossley ran thermal simulations of the stacked module with three different potting compounds. There are two hotspots on the lower circuit board at about 92 C caused by two phase lock loop (PLL) devices. There are also two hotspots on the upper circuit board produced by another PLL at 88 C and the TSB41BA3 device also at 88 C. The performance of all three potting compounds was simulated. “Thermal simulation gave us the best of both worlds by identifying an optimized solution while minimizing our engineering costs and lead time,” Hunt concluded.

For more information, visit This article was submitted by Mentor Graphics in Wilsonville, Ore.

Tom Litrenta is an engineer with GE Fanuc Intelligent Platforms.

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