By John McHale
COSTA MESA, Calif. - Experts from industry and academia have joined hands to design a chip that combines 3D-stacked packaging and fast electronic interconnects, as well as optically switching parallel interconnections, to turbocharge computing speed while reducing component size and power consumption.
Members of the consortium, based at the University of California at San Diego (UCSD), are developing a parallel, optically switched processor core for computers under a cooperative agreement with the Defense Advanced Research Projects Agency (DARPA).
The goal is to combine 3D stacking technology with high-speed digital connections using vertical-cavity surface-emitting lasers.
The heart of the new technology is a combination of the electronic densities available with chip-stacking processes from Costa Mesa, Calif.-based Irvine Sensors Corp., and the speeds possible with optically switching parallel interconnections between separate chip stacks.
Experts say the new approach will permit a breakthrough in processing speed for classes of applications that are presently limited by computer bus architectures.
Consortium scientists say they believe this developmental hardware - which will use future deep sub-micron technologies - will pave the way to the near-term use of optical interconnects in military systems for substantially improved portability and performance.
"The demand for optical switching is being driven by the need for low-cost gigabit networks," says J. Bruce Totty, corporate director of sales and marketing at Irvine. "Optical interconnects and switching are believed to be the key enabling technologies to achieve speeds which will in turn impact a wide range of applications including servers, portable computer systems, high-speed telecommunications switches, cable TV and fiber optics-to-the-home."
To get there, however, requires a new level of technology. "Available board-level architectures can`t handle optical parallel switching at useful levels of density," says John Carson, senior vice president and chief technical officer at Irvine. "Our 3D Silicon stacking technology can.
"The consortium`s goal is to exceed a terabit-per-second processing speed in a volume of a few cubic inches," Carson continues. "To meet that goal, we need to demonstrate a number of `firsts` under this contract including the integration of a novel optical switching array with stacked processors, a record number of such stacked logic chips, and an order of magnitude improvement in heat extraction technologies necessary for such stacks."
Within chip stacks, each chip communicates with its neighbors using electrical interconnects deposited on the sides of the stack. This approach reduces the length of the chip-to-chip interconnects by placing adjacent chips in close proximity.
When a system consists of several stacks, scientists plan to use optoelectronic interconnections due to their power-delay advantage over their electrical counterparts at room temperature. In this case, free-space optics provide the much-needed low power, global high-density interconnects to pass data between chips in large stacks or between stacks.
In particular, consortium engineers will focus on providing optoelectronic interconnections to 3D chip stacks using vertical-cavity surface-emitting laser arrays with associated drivers, specially designed optical receivers, and micro-optics to direct the optical signals between the stacks.
Diamond substrates interleaved between the chips capable of dissipating more than 300 watts per stack will increase power, explains Volkan Ozguz, Irvine`s manager of 3D Silicon R&D and the principal investigator of the optical interconnect program.
The Irvine packaging reduces the size of the current system by 50 times, says Ozguz.
"With a prototype processor we will shoot for 16 by 16-bit DSPs to 32 by 32-bit DSPs that are optically connected to a second stack of electronic crossbar chips, says Phillipe Marchand, a project coordinator at UCSD.
"Over the next two years standard workstations, Pentiums, etc., will increase 10 to 20 gigabits; we hope to increase speed to at least 256 gigabit per second," Marchand says.
The optoelectronic solution that the consortium engineers will implement for a parallel fast Fourier transform machine is based on integrating a compact optical transpose interconnection system together with two functional stacks that will perform the necessary computations as well as implement the required local switching.
Typical problems that occur with the new technology include heat buildup in the stacks, misalignment of the chips, and customizing off-the-shelf equipment, Marchand explains.
"We can`t use off the shelf products; we must redesign chips, SRAM etc.," he says. Irvine engineers are reducing heat buildup by using low-power memory chips and special heat-conducting packaging materials.
Micro electromechanical systems technology will help solve the alignment problems by using an ion etching process, Marchand says.
Another area of concern is manufacturing yields on the arrays, Marchand notes. "All throwaways must be eliminated before we go commercial with the device. We will need a 99.9999 percent yield on the arrays."
The DARPA-sponsored consortium includes University of California at Los Angeles, the Georgia Institute of Technology in Atlanta, the University of Pittsburgh, the University of North Carolina at Charlotte, and the University of California at Santa Barbara, the Honeywell Technology Center in Minneapolis, Mercury Computer Systems in Chelmsford, Mass., Sun Microsystems in Mountain View, Calif., Kopin Corp. in Taunton, Mass., and Cascade Design Automation Corp. in Bellevue, Wash.
For more information contact the consortium on the World Wide Web at http://soliton.ucsd.edu/3doesp/.
A consortium of experts from industry and academics based at the University of California at San Diego are designing a chip that combines 3D stacking processes and optically switching parallel interconnections. Above are the schematics of stack to stack free space optical interconnects (FSOI)interconnected FFT engine.
