Actel SPGAs shrink designs in tight spaces

June 1, 1997
SUNNYVALE, Calif. - Engineers at Actel Corp. in Sunnyvale, Calif., are offering a new class of SRAM-based application-specific integrated circuit (ASIC) called the System Programmable Gate Array (SPGA).

by John McHale

SUNNYVALE, Calif. - Engineers at Actel Corp. in Sunnyvale, Calif., are offering a new class of SRAM-based application-specific integrated circuit (ASIC) called the System Programmable Gate Array (SPGA).

Engineers developed the SPGA to address the new requirements for field-programmable gate arrays (FPGAs) such as dramatically increased capacity, architectural efficiency, predictability, and support for system design features that they cannot satisfy simply by adding gates or tweaking tools.

"When left unaddressed, these unresolved requirements become design issues that grow exponentially as design complexity increases," explains Robert Nalesnik, Actel`s director of product marketing in a SPGA technology background report.

"To successfully integrate intellectual property - whether created in-house or developed by a third-party IP provider - a new class of programmable device, the SPGA, with higher in-system performance, greater logic capacity, and more predictable performance is required," he says.

SPGAs are expected to be particularly appealing to military and aerospace electronics designers because of their high level of integration. One SPGA is expected to do the jobs of several of the current generation of programmable devices, and will help enable designers to pack more capability into smaller spaces - a big benefit where space and weight are critical concerns, such as missile guidance and avionics.

"Today, the entire semiconductor industry is being transformed to accommodate the demands of an explosive new market best defined by the phrase `system-level design,``` Nalesnik says.

"Current FPGA technology alone cannot satisfy the requirements of this new and potentially much larger universe of designs. Significantly, standard ASIC technology also falls short of these requirements."

Nalesnik defines high capacity as the requirement for dramatically increased capacity as the fundamental requirement of system-level design. System-level designs demand device capacities ranging from 50,000 to more than one million gates. However, the capacity limit of current FPGA technology is in the 100,000 to 120,000 gate arena.

He says architectural efficiency assumes no changes to current FPGA architectures; a 2-million-gate design would be physically too large to be cost-effectively manufactured. In fact, a design of this size would be too large to manufacture at all, given current lithography tools. The only way to resolve this dilemma is to completely redesign the architecture to support greater levels of integration.

Predictability, Nalesnik says, involves system-level design requiring an architecture able to remain predictable throughout the design cycle, even after significant changes. FPGA designers recognize that predictable timing - if it could be realized - would dramatically reduce design time.

IP Integration is the ability to integrate intellectual property from several sources into FPGA architectures, and is a critical but currently unsupported requirement of system-level design, Nalesnik says. Designers want the flexibility to integrate hard-wired cores or hardware description language-based functional blocks into their designs at various points in the design process, he points out. This capability should also be software-independent, supporting both the VHDL and Verilog design languages. Combined, these capabilities enable design re-use for quick and easy implementation of multiple product versions.

At the device level, new products for system-level design must include support for common system functionality, Nalesnik says. This kind of support includes: on-chip digital phase locked loop for synchronizing several clocks and implementing complex, high-frequency clocking schemes; interface flexibility for supporting industry-standard interfaces, varying power requirements, and adjusting slew rates; test and debug features for fast and accurate device reliability testing and isolation of system bugs; efficient routability for easy porting of soft IP to the system design; and design security for protecting intellectual property.

System-level design with SPGAs includes highly integrated functionality that, in the current generation, would require multiple devices, Nalesnik says. "By any definition, system-level design will enable a new world of devices, many of which have yet to be envisioned."

"Most insiders agree that system-level designs will require device capacities of 50,000 to one million gates or more in the future," Nalesnik continues. "In the past, this high capacity was only available from ASIC devices. However, ASICs require mask programming cycles of several weeks or more, pushing market windows to the limits of acceptability and putting millions of dollars of potential market share at risk."

Current FPGA technology is less than ideal for system-level applications - "in fact, if they were reinvented today with system-level design in mind, current FPGAs would look entirely different," Nalesnik says.

SPGA products

Actel officials offer two SPGAs: ES Reprogrammable and ES Reprogrammable Embedded SPGAs. Both are for system-level applications such as telecommunications, industrial control, high-speed networking, gate-intensive graphics processing, and high-performance hardware emulation. Actel SPGAs support HDL-based soft cores and hard-wired ASIC cores, including SPGA-optimized functions from third-party IP providers.

Actel`s new family of ES reprogrammable SPGAs offers from 25,000 to 400,000 available logic gates. The ES Reprogrammable SPGAs feature structured, synthesizable logic cells, with as many as eight hierarchical levels of segmented routing tracks with reprogrammable SRAM interconnect.

Actel`s ES Embedded SPGAs consist of an embedded Cell Based Array (CBA) implementing complex system elements such as third-party intellectual property cores, or system-level functions developed in-house by customers. Surrounding the CBA are programmable logic and interconnect based on Actel`s ES Reprogrammable SPGAs.

CBA is a gate array architecture with efficiencies approaching full-custom circuit designs. Actel officials have licensed the Synopsys CBA architecture in a joint development for their new families of SPGAs. Major gate array vendors have licensed CBA, including Fujitsu, Hewlett-Packard, Hitachi, IBM, Matsushita, NEC, and Toshiba.

E-mail to [email protected] for more information on Actel SPGAs.

Voice your opinion!

To join the conversation, and become an exclusive member of Military Aerospace, create an account today!