Avionics design hits the fast track
The COTS approach brings burgeoning choices and ever-quickening turnover between successive device generations, leaving aviation electronics engineers hard-pressed to take advantage of the best technology has to offer
The COTS approach brings burgeoning choices and ever-quickening turnover between successive device generations, leaving aviation electronics engineers hard-pressed to take advantage of the best technology has to offer
By John Keller
Avionics designers for military and commercial aircraft face a dizzying array of component choices as government and industry move inexorably toward commercially developed technology and start to abandon custom-built equipment that has long been the mainstay of airborne electronics.
That is a blessing and a curse. As choices multiply, designers come under increasing pressure to accommodate rapidly changing technology to keep pace with their brethren in the commercial electronics sector, where technological generations can turn over every 18 months, or even faster.
The need to blend in new generations of components in an ever-quickening spiral produces no small level of anxiety among military and aerospace electronics builders, and points to one of the most striking distinctions in how military and commercial engineers approach their designs: commercial systems operate for a few years before users replace them; military systems, on the other hand, must bring substantial capability to the field for as long as a half century - particularly as the Pentagon`s share of the federal budget decreases. In the future Pentagon experts expect them to operate for even longer.
With this in mind, one of the chief worries keeping military and aerospace engineers awake at night is how to build airplanes that retain the same airframes essentially for decades, but that are capable of accepting dozens of new generations of electronic technology throughout their lifecycles.
Certainly, many tried-and-true component technologies from the recent past will have a place - albeit in diminishing roles - in avionics suites of the future. Prime examples are the SEM-E printed circuit card form factor and PiBus backplane data bus, the MIL-STD 1553B serial data bus, and the MIL-STD 1750 16-bit processor.
The Northrop Grumman B-2 stealth bomber, for example, is using the traditional 1750 processor, SEM-E circuit cards, and 1 megabit-per-second 1553 data bus in its latest "Block 30" avionics configuration. Few, if any, commercial off-the-shelf (COTS) components are in the plane`s avionics due to radiation-hardness requirements. Still, the B-2 will not avoid coming under the influence of the COTS design philosophy.
The COTS influence
Air Force leaders have asked Northrop Grumman engineers to look into COTS components for future B-2 avionics processing needs. "This past winter and spring we performed a company study of COTS for the B-2 to address obsolescence problems, the main objective of which would be to reduce the cost of ownership for the Air Force," explains company spokesman Ed Smith. "We shared this study with the Air Force and they asked us to put together another study including a COTS application end demonstration."
Northrop Grumman engineers are set to complete a statement of work outlining the study by July or August, Smith says. No further details on B-2 COTS avionics integration was available.
Yet as designers continue to embrace COTS components for avionics at a quickening pace, other technologies that either have broad industry backing or that offer technological advantages that simply cannot be ignored are making their way into new airborne platforms and into upgrades to existing aircraft.
Examples of component technologies that designers until recently had not dreamed would ever be part of their avionics architectures include the VME-64 6U printed circuit card form factor and backplane data bus, the Fibre Channel high-speed fiber optic serial data bus, and the Apple/IBM/Motorola PowerPC 32-bit micro-processor. Even the Digital Alpha and Intel Pentium microprocessors and Futurebus+ backplane data bus have cropped up in some designs.
Suffice it to say that the imperative to reduce procurement and maintenance costs for avionics, coupled with the need to rapidly insert powerful new technology as industry makes it available, are driving today`s avionics designs. And there will be few opportunities for designers to stop for a breather. The trend to COTS undoubtedly will accelerate in the near future.
Joint Strike Fighter
Crowning the military`s switch to COTS-based avionics is the Joint Strike Fighter (JSF), a planned supersonic multi-role combat jet being built to replace the U.S. Air Force Lockheed Martin F-16 fighter, the U.S. Navy Northrop Grumman A-6 bomber and F-14 fighter, the U.S. Marine Corps. McDonnell Douglas F/A-18 fighter-bomber and AV-8B jump jet, and the U.K. Royal Navy British Aerospace Sea Harrier jump jet. Four words perhaps best describe the ambitious goals of JSF avionics specifiers: affordability, capability, upgradability, and reusability.
"The architecture will utilize COTS technology to the maximum extent possible for all aspects, including processing and network architectures," according to a statement from officials of the Boeing Military Airplane Co. in Seattle, in response to written inquiries. Boeing is one of two JSF competing contractors. "This architecture will also utilize open-system standards for network, operating system, and application program interfaces to increase application software portability and extensibility."
Keeping costs to a minimum is one of the primary goals of the design. "The main objective in utilizing COTS and open-systems standards is to increase software longevity, to insulate the system from hardware technology obsolescence, and to make upgrades far easier and cost effective," according to the Boeing statement. "Using these technologies will allow us to make key hardware decisions far later in the development cycle. Implementing processor and network decisions `just in time` will maximize the use of the latest technology, provide longer process life-cycles between technology upgrades, and will greatly reduce the lifecycle development costs."
To put a point on it, "nothing gets on the aircraft unless it is affordable," says Navy Cmdr. Chris Evans, the integrated processor team leader at the JSF Program Office in Arlington, Va. The two contractors competing to build the JSF - Boeing, and Lockheed Martin Fort Worth Division in Fort Worth, Texas - are releasing specifics of the JSF avionics architecture that are sketchy at best, not only because military officials want to hold the design open as long as possible to avoid specifying obsolescent techno-logy, but also because of competition sensitivity between two JSF contractors.
Designers are seeking to craft avionics for the JSF that not only can integrate onboard and offboard data sources, deliver precision-accurate weapons in all weather and at night, and detect and diagnose mechanical faults during flight, and help evade enemy air defenses, but also that lends itself to quick and easy upgrades, and could fit into a wide variety of aircraft. The JSF also is expected to have an advanced automated fault-detection system.
"The main cost is in the application software, so we want a computer from where we can port software and perhaps some hardware to another aircraft if possible," says Air Force Maj. Lynne Hamilton-Jones, integrated core product lead in the JSF office. "We are looking at a common programming language, Ada 95, and converting Ada 83 to Ada 95 code. Ada can reduce the overall lifecycle costs and I believe our contractors are committed to Ada."
On the mechanical/electrical level, JSF officials are considering the SEM-E printed circuit card form factor - for the moment. "SEM-E is the baseline, but that may change," Hamilton-Jones cautions. Industry sources suggest that VME may quietly be replacing SEM-E in JSF planning. They bring up the JSF imperatives for low cost and broad support- ability, and point out that VME boards are less expensive and far more broadly supported in industry than are SEM-E boards.
The JSF`s engineering and manufacturing development (EMD) phase - the final stage before production - is set for mid-2001, and between now and then officials from the JSF office and the contractors are seeking to reduce design risk in all avionics componentry, she says.
For inter-subsystem networking, JSF contractors are considering a wide variety of high-speed data buses, including Fibre Channel, the Scalable Coherent Interface - better known as SCI - Serial Express, Asynchronous Transfer Mode -or ATM - Myrinet, and S-Connect, Hamilton-Jones says. There is no clear-cut frontrunner, she insists, despite a recent surge in industry momentum behind the 1 gigabit-per-second Fibre Channel data bus (see story page 16).
Decisions on microprocessors and digital signal processors for the JSF will remain open at least for the next several years. "We really don`t care about CPUs and DSPs now," Hamilton Jones says. "That will come later for EMD." In fact, JSF avionics designers are striving to craft an architecture that could seamlessly accommodate many different microprocessors. Whether that can happen remains to be seen. "We would like to be processor-independent, but that is hard," Evans admits. "We don`t want to make commitments too early."
One driving consideration in JSF avionics research is to learn from past mistakes. "We have learned not to look into commercial standards that we cannot adapt to new technology," Hamilton-Jones explains. She gives the example of the venerable 1553 serial data bus, which she says "does not have a clear upgrade path."
Many electronic technologies, officials point out, simply will not last for the projected life of the JSF aircraft, which forces engineers to become educated fortune tellers, and predict future major upgrades and accommodate them as early as possible in the aircraft`s initial design. "You won`t build a 50-year backplane for this airplane, or a processor that will last more than 18 months," Evans warns. "We are taking our best shot at this."
The JSF avionics effort in many ways can be considered to be a refinement of many existing avionics design initiatives. The lessons learned from aircraft programs such as the Lockheed Martin F-22 Raptor fighter, the Boeing-Sikorsky RAH-66 Comanche scout-attack helicopter, the McDonnell Douglas F/A-18E/F fighter-bomber, the Boeing B-1 bomber, and McDonnell Douglas AH-64 Apache attack helicopter not only feed to and from one another, but all in some ways lead into JSF avionics planing.
The wave of COTS technology that is inundating avionics design workbenches is beginning to force engineers to alter their original designs sometimes even before prototyping, but often before programs enter production.
Take the RAH-66 scout-attack helicopter. The original 1991 avionics baseline called for the Intel 80960 microprocessor, an SAE-standard 50 megabit-per-second linear passive star fiber optic data bus from Harris Corp. of Melbourne, Fla., SEM-E circuit cards, and the PiBus backplane data bus. Ensuing circumstances, however, swept a portion of the Comanche`s avionics foundation out from under its designers.
Today much of the Comanche`s original design remains intact, except for the central processor. Because of recent decisions at Intel to stop producing mil-spec devices, along with tremendous increases in the capability of PC microprocessors, engineers at the Boeing Defense & Space Group Helicopters Division in Philadelphia scrapped the i960 in favor of the Intel Pentium 133 MHz microprocessor.
Boeing avionics designers ran into similar issues on the U.S. Marine Corps Bell-Boeing V-22 Osprey tiltrotor aircraft. The avionics design for EMD versions of the V-22 specify the Advanced Mission Computer (AMC) from Computing Devices International in Minneapolis. The AMC features the MIPS R-4000 microprocessor, 10 SU printed circuit cards, the Futurebus+ backplane data bus, and 1553 serial data bus.
What designers didn`t count on in their early planning, however, was the lack of industry support for Futurebus+. Highly touted in the late 1980s and early 1990s as a replacement for the VME backplane data bus, Futurebus+ failed to gain strong industry support, particularly in the wake of bandwidth improvements to VME.
"We are now proposing elimination of the Futurebus+ configuration" on advanced versions of the V-22, says Feliks Bortkiewicz, lead software engineer on V-22 project at Boeing Helicopter. Instead, designers want to eliminate inter-module communications in V-22 avionics, use one R-4000-based single-board computer per AMC box, and use the space that Futurebus+ interface cards previously occupied for additional memory, says Steven Goldman, Boeing`s manager of V-22 avionics.
Boeing engineers are locked into the Futurebus+-based EMD avionics design for four aircraft, but seek to scrap Futurebus+ on the so-called CV-22 for special-operations forces. The CV-22 will have terrain-following radar and a newer electronic warfare suite than the EMD version of the aircraft, referred to as the MV-22.
The MIPS microprocessor architecture, designed by MIPS Technologies Inc. of Mountain View, Calif., and available from several different microprocessor vendors, has other champions among avionics designers in addition to Boeing and Computing Devices. This 32-bit RISC microprocessor architecture also is to be part of upgrades to the AH-64 Apache helicopter and the F-16 Mid-Life Upgrade.
Designers of planned upgrades to the Boeing B-1 swing-wing bomber, meanwhile, are considering widely available COTS technology to be a big opportunity. The B-1 avionics overhaul represents one of the most substantial moves to COTS in all U.S. military avionics.
Engineers at the Lockheed Martin Federal Systems in Owego, N.Y. - under contract to Boeing North American in Seal Beach, Calif. - are replacing six existing custom-design computers on the B-1 with four new computers that will provide 25 times the throughput of the aircraft`s avionics as it is deployed today.
The new B-1 core avionics will be based on the PowerPC microprocessor, VME 64 backplane data bus and 6U circuit cards, an on the Fibre Channel high-speed data bus.
Not only does the B-1 upgrade represent a bold transition to COTS technology, but its avionics suite also is to exemplify a new wave in inter-subsystem avionics communications by using different serial data buses for separate applications - many of them with built-in redundancy for enhanced reliability.
The upgraded B-1 will feature eight redundant 1553B data bus interfaces and two arbitrated-loop Fibre Channel interfaces. Designers are expected to employ the old reliable 1553 for low-throughput, flight-critical tasks such as controlling landing gear, lighting, and aircraft control surfaces, and the state-of-the-art 1-gigabit-per-second Fibre Channel for high-throughput tasks such as imaging, digital signal processing, and automatic target recognition.
B-1 designers are not alone in their choice of the PowerPC for new avionics architectures. Engineers at the AlliedSignal Aerospace Guidance & Control Systems division in Teterboro, N.J., have settled on PowerPC to drive the avionics of the next-generation NASA space shuttle called VentureStar.
Under contract to Lockheed Martin Corp. of Bethesda, Md., VentureStar will have identical computers integrated into four separate boxes called Vehicle Mission Computers. Each box has PowerPC based VME single-board computers to handle flight control, mission control, and utility management. Connecting each computer box will be the 1553B data bus.
The Alpha microprocessor from Digital Equipment Corp. in Marlborough, Mass., has its share of design-ins, most notably aboard the latest versions of the Northrop Grumman Air Force E-8 Joint Surveillance Target Attack Radar System aircraft - better known as Joint STARS - and the Navy E-2C Hawkeye carrier-borne surveillance aircraft known as "Hawkeye 2000," which is undergoing flight testing.
The Hawkeye 2000, the more recent of the two projects, features the Model 940 system from Raytheon Electronic Systems Division in Marlborough, Mass. Raytheon engineers, drawing on the experience they gained a decade ago in the so-called "Mil-VAX" program, ruggedize the Digital Model 2100 VME System in their Model 940, which is based on the 21164 250 MHz Alpha chip.
The multiprocessing system can handle from one to four CPU VME boards and passes data in a variety of ways. Data passing between processors and between solid-state memory runs on Digital`s Cobra data bus. Data passing between mezzanine cards and VME cards runs on PCI bus, while serial data passing between subsystems runs on any of three buses - 100 megabit-per-second fast Ethernet, 16 megabit-per-second Ethernet, or 1 megabit-per-second 1553, says Lawrence Rainville, program manager of the E-2C mission computer program at Raytheon.
Crew members of the Navy Northrop Grumman E-2C radar aircraft can monitor 6 million cubic miles of air space and more than 150,000 square miles of ocean surface. The aircraft`s avionics is receiving upgraded computers based on the Digital Alpha 64-bit microprocessor.
The Joint Strike Fighter is expected to be a showcase of commercial off-the-shelf electronics components, and is widely expected to receive the Fibre Channel high-speed data bus as well as either VME or SEM-E printed circuit cards. Pictured above is an artist`s rendering of the Boeing version of the new aircraft.
The avionics bus wars: Fibre Channel moves solidly in front
Industry-standard high-speed avionics data buses capable of running over copper wire or optical fiber have never been more numerous. The list of candidates includes the Fiber Distributed Data Interface, or FDDI; Asynchronous Transfer Mode, or ATM; the Scalable Coherent Interface, or SCI; fast Ethernet; Serial Express; S-Connect; Fire Wire; and others.
Until recently, however, none of these buses has moved via industry consensus to top of almost every avionics designer`s list. That is, until the breakout emergence of ANSI X-3.230-1994 Fibre Channel, a 1 gigabit-per-second bus that experts say is blowing by its competitors as the serial network of choice in the high-performance avionics business.
Fibre Channel is already part of the design baseline for avionics upgrades in the McDonnell Douglas F/A-18 Hornet fighter bomber, the McDonnell Douglas AH-64 attack helicopter, the Boeing North American B-1 Lancer strategic bomber, and the Boeing Airborne Warning and Control System aircraft known as AWACS.
Programs where officials reportedly are considering Fibre Channel seriously include the TRW Joint Airborne SIGINT architecture, and perhaps most significantly the Joint Strike Fighter.
"Fibre Channel has some incredible momentum right now," says Don Spolar, data bus product marketing manager at semiconductor vendor ILC Data Device Corp. in Bohemia, N.Y.
"I don`t know if there are drawbacks to Fibre Channel," says Tom Bohman, product strategist, at Systran Corp. in Dayton, Ohio, a COTS supplier of Fibre Channel interface cards and drivers. "It is a little less mature in the driver area than ATM, and the drivers that control upper level protocols are perhaps not as mature, but they are coming along quickly. I would say the momentum of Fibre Channel is very strong."
Fibre Channel is emerging as the strongest candidate to replace the venerable MIL-STD 1553 1-megabit-per-second serial data bus that has been in wide use aboard military aircraft for the past 20 years. Although designers are reluctant to part with 1553, they realize that new avionics capability involving images, video, and multiband communications will overwhelm 1553`s bandwidth.
"Fibre Channel is used wherever throughput is a problem, and that is anywhere where you deal with image processing, radar, sonar, video, any of those kinds of high-bandwidth data acquisition/data transport problems, and anywhere there is need for high-speed mass storage," Bohman says.
"Something ATM doesn`t begin to offer is that kind of flexibility," he continues. "In terms of reliability of data transfer, end to end flow control, and actual throughput, Fibre Channel really has many advantages over ATM."
The rise of Fibre Channel, however, does not necessarily signal the end of 1553. Quite the contrary, experts believe; Fibre Channel and 1553 are expected to exist side-by-side in avionics designs for many years to come.
"All our research projects that 1553 still has a 20-year life because many functions of a plane will not have a need for high speed, such as flight surfaces, landing gear, munitions, and other rudimentary functions," explains ILC`s Spolar.
"Platforms of the future will have multiple buses, high speed and low speed," Spolar says. "1553 is not going anywhere. We guarantee that to our customers. The goal is to have multiple buses, with 1553 doing rudimentary tasks where Fibre Channel would have problems with slow applications. We want to keep the Volkswagens on the Volkswagen road and the Ferraris on the Ferrari road, with separate data paths." - J.K.
The Systran FibreXpress Network PMC interface card for the Fibre Channel 1 gigabit-per-second data bus is expected to play a substantial role in avionics designs of the future.
New trends in avionics packaging, test
Avionics design at the component level is seeing new trends in packaging and test, say officials of National Semiconductor Corp. of Santa Clara, Calif., one of the major U.S. suppliers of military application-specific integrated circuits (ASICs), interface silicon, and analog devices such as A-D converters and high-speed op amps.
"We are seeing a greater leaning toward more and more surface mount, and less through-hole packaging," says Brad Paulson, marketing director for the National Semiconductor Mil/Aero Division.
Another component trend in avionics involves built-in test. "We are seeing an emphasis on boundary scan IEEE 1149.1 in self test and in the stand-alone monitor for printed circuit boards," Paulson says.
The 1149.1 standard, also known as the Joint Technical Assessment Group testing - or JTAG - is a non-intrusive method of testing predominantly digital circuit boards and components.
"We manufacture the scan product from 1149.1-compliant JTAG products for in-system monitoring," Paulson says. "We incorporate that as a system cell so people can build it into our ASIC or in ASICs they design themselves. It is on the F-22, the RAH-66 Comanche, and I would think it will have a role in the JSF [Joint Strike Fighter]."
Paulson says National`s JTAG cells are incorporated into multichip modules with I/O functionality "so you can see which chip is bad." These cells are designed into the McDonnell Douglas F-15E and F/A-18 E/F fighter bombers, as well as in the Boeing 777 jetliner. - J.K.