Parallel video DSP chip aims to compete with TIs C80

SHELTON, Conn. - A parallel video digital signal processing (DSP) chip from Oxford Micro Devices Inc. in Shelton, Conn., will give the Texas Instruments TMS320C80 DSP a run for its money if the Oxford device actually works as its inventor claims when the first silicon becomes available in January 1997.

Jan 1st, 1997

By Kelly Sewell

SHELTON, Conn. - A parallel video digital signal processing (DSP) chip from Oxford Micro Devices Inc. in Shelton, Conn., will give the Texas Instruments TMS320C80 DSP a run for its money if the Oxford device actually works as its inventor claims when the first silicon becomes available in January 1997.

The Oxford A236 DSP and the C80 will have similar performance at similar cost, claims Steve Morton, Oxford`s president, chief executive officer and the A236 inventor. Yet he says his device will be simpler to manufacture and program.

"We have gate-level simulations in the lab," Morton claims. "We designed it in VHDL. We synthesized it into Samsung`s gate-level library. So we know it works; gate-level simulation is the last step before it goes to Samsung Electronics [the foundry].

Several industry observers frankly doubt that Oxford engineers will succeed in building a DSP that meets company claims. Morton himself admits he has reservations, but is optimistic of ultimate success. "Maybe we`ll screw up. But we`re hopeful it will work so we can get into subsequent revisions."

Morton has been developing the A236 since he started the company in the late 1980s. With money from venture capitalists, as well as U.S. government small business innovative research (SBIR) contracts of $50,000 and $707,000, Morton says he was able to get the product off the ground.

The SBIR money came from the U.S. Army Communications-Electronics Command (CECOM) Night Vision labs in Fort Monmouth, N.J., for neural network research for a helicopter missile-avoidance program.

As Morton completed the research, the neural network project evolved into the current general-purpose DSP chip. The contract is still active and Morton will deliver the first chips and an evaluation board to CECOM officials when available.

The programmable A236 Parallel Video DSP Chip is intended for high-volume, low-cost, high-performance real-time applications. It is programmable in C, uses enhanced single-instruction/multiple data processing, has four 16-bit vector processors, one 24-bit scalar processor, real-time video I/O and processing, requires little or no glue logic, has a fast, low-cost memory system, two 16-bit video-aware direct-memory-access (DMA) ports, and one 16-bit DMA data/command port.

"We`ve designed for simplicity," Morton says. "It`s a vanilla 0.6 micron double metal standard cell CMOS process." In comparison, the C80 is three layers.

The C80 uses multiple instruction/ multiple data processing, and Morton claims it is difficult to program. So he designed his chip to be easier to program than the C80, with simpler interfaces, and a multimedia CD-ROM training course.

The C80 and the A236 can process as many as 2 billion operations per second, although the 60-MHz C80 is as fast as 2.5 billion, says Rick Rinehart, C80 program manager at TI`s Semiconductor Division in Houston.

While skeptics say they`ll believe in the A236 when they see it, Morton claims there are major companies ready to buy once he can produce the chip. Potential applications include satellite image processing, radar systems, surveillance systems, as well as several commercial applications.

"We built the A236 chip from the ground up," Morton says. "It has four, clearly identifiable, 16-bit processors with many registers and enhancements. And instead of a simple load-store architecture, it can read memory and operate upon the data at the same time, or operate upon data and write it to memory at the same time, which improves performance."

Morton says the A236 supports only synchronous dynamic random access memories (DRAMs), and synchronous graphic DRAMs can also be used in synchronous DRAM mode. The nominal clock frequency is 100 MHz, with bursts as large as 400 Mbyte/s.

The minimum requirement for system implementation is an A236, one 32-bit synchronous graphic DRAM, a serial electronically erasable programmable read-only memory (EEPROM), a clock for the central processor (nominally 40 MHz), a clock for the memory interface (nominally 100 MHz), and peripheral devices.

Designers can connect several A236 chips in series, in parallel, and in series- parallel arrays by their parallel DMA ports. Each A236 chip has its own external memory and serial EEPROM.

Programmers can code the A236 chip in either Assembly language or in Oxford`s parallel-enhanced version of C, which is ANSI-compatible. "The A236 chip and our C compiler were designed together to make it as easy as possible to program the A236 chip in C," Morton says.

But TI`s Rinehart says he is skeptical as to how much of a threat Oxford will be. He claims TI`s support is superior. "We offer a 4-day training session for the developers, which us more than downloading a read-me file off the Internet," he says, referring to Oxford`s software, which is available for free on the company`s World Wide Web home page (http://www.oxfordmicro-devices.com).

In addition, when the C80 moved to a 60-MHz clock rate, company officials switched to a 0.5 micron fab process, which dropped the power by 40 percent.

TI engineers also have reduced power and volume of the 60-MHz C80, and use- ball grid array instead of pin grid array packaging. "It`s much cheaper and does a better job from a thermal point of view, since it doesn`t require heat sinks with these clock rates," Rinehart says.

Indeed, the C80 is now as inexpensive as the A236, both available for less than $100 in quantities of 100,000.

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