Adaptive computing has arrived

May 1, 2001
Reconfigurable computers, chips or systems that alter their personality to adapt to changing applications, are becoming reality.

By John McHale

Reconfigurable computers, chips or systems that alter their personality to adapt to changing applications, are becoming reality. The improved performance of field programmable gate arrays and software tools has paved the way for designers to create systems that reconfigure themselves on the fly, thereby improving performance and mitigating obsolescence.

WildFire FPGA boards from Annapolis Micro Systems use Xilinx FPGAs to provide 10 times the performance of a typical DSP board, Annapolis officials claim.
Click here to enlarge image

Today's electronic warfare designers have used commercial-off-the-shelf (COTS) microprocessor technology to create systems that use so much computational power that they can track targets on land, sea, or air, and determine whether the target is friend or foe. All of that is about to change with the advent of adaptive, reconfigurable computing.

Adaptive computers, systems that can reconfigure their circuits during operation to adapt to new tasks or failed components, promise to be 100 to 1,000 times faster than microprocessor-based systems, creating a revolution in computing. The reconfiguration would be done through software tools on COTS devices called field programmable gate arrays (FPGAs).

Adaptive computing is the next step in the evolution of computers, says Ray Alderman, executive director of the VME International Trade Association in Scottsdale, Ariz. The technology is part of the move from sequential processing to parallel processing, he adds.

Sequential processing is a processor, such as a Pentium, K-62, or PowerPC, performing tasks in a specific order, one after another, while parallel processing performs tasks concurrently, Alderman explains. Today's multiprocessing systems are a step in the parallel direction, with many different processors doing the same tasks at the same time, Alderman continues.

Adaptive computing systems will involve computers that can morph their personalities based on the tasks at hand, whether it is performing Fast Fourier Transforms (FFTs), handling interrupts, or on a larger scale — reconfiguring sensors in a radar or sonar system based on changing mission parameters, he says.

Radar, sonar, target recognition, terrain mapping, and image processing systems will benefit most from this technology. Designers of these systems will be able to place the capability of a large multiprocessing system onto small FPGAs, Alderman says. The processing will be done in parallel in hardware on FPGAs, he adds.

The key to for unlocking the adaptive powers of FPGAs is soft hardware, he continues. Soft hardware provides the capability to program logic onto FPGAs through VHDL (VHSIC Hardware Description Language) on intellectual property (IP) cores, Alderman explains.

The cores will represent the intellectual property of a digital signal processing (DSP) chip, PowerPC processor, Pentium device, etc., enabling the FPGA to perform the functions of the particular hardware device in a smaller space and with greater performance, he says. They will also be easy to upgrade and reconfigure because their functions can be programmed into the hardware on the fly, Alderman adds.

The military may embrace reconfigurable computing slower than the commercial world, but they will embrace it, because of the obvious size and weight advantages of an FPGA as well as its ability to mitigate obsolescence, says Steve Paavola, director of marketing at Sky Computers in Chelmsford, Mass.

Engineers at Sky see reconfigurable computing offering advantages to military multiprocessing applications such as synthetic aperture radar (SAR), he says. Military personnel will be able to reconfigure the SAR system quickly whenever the mission requirements change, Paavola continues. For example on an unmanned aerial vehicle surveillance mission, operators may have to reconfigure the sensors on the fly based on changing mission parameters, weather conditions, etc., he says.

Sky engineers produce multiprocessing systems based the Motorola PowerPC 7400 AltiVec chip for applications such as sonar, radar, as well as SAR. They are currently being evaluated for the Aegis radar upgrade.

Fault tolerance

Another advantage that reconfigurable computing can bring is fault tolerance, Paavola says. In other words the ability to identify components that are failing and configure the system to work around them, he explains.

This is not a new concept and can be cost-effective in terms of maintenance and reliability issues, Paavola says.

U.S. Navy officials say they want their future ships to be able to go out to sea for six months at a time with less crew and less maintenance personnel, Paavola says. Computer systems that can configure around faulty hardware will save money and time by not only cutting down on crew training but also minimizing downtime, he adds.

Another name for this concept is "self healing," says Steve Guccione, senior staff engineer at Xilinx in San Jose, Calif. Xilinx engineers are also researching fault tolerance for possible use by the military and other markets.

The idea is pretty straight forward, Guccione says. FPGAs on a board isolate faults, then reconfigure in a way that works around the faulty component, he explains. In other words they heal, Guccione adds.


Traditionally FPGAs have always been a more expensive solution than an application-specific integrated circuit (ASIC). In fact, there was an old axiom that if you had an order for 10,000 units or less, go with a FPGA. If you had more than 10,000 orders, stick with the ASIC, it will cost less on the front end.

Varicore devices from Actel are embedded programmable gate array blocks are "soft hardware" core tiles based on a three-input look-up table.
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All chips are ASICs, says Steve Scalera program manger at BAE Systems' Information and Electronic Warfare Systems unit, formerly Sanders, in Nashua, N.H. A FPGA is an ASIC as is a Pentium chip, he adds.

FPGAs started out as prototypes for ASIC designs, Scalera says. A designer would test out a particular design on an FPGA, then move it to an ASIC when it was ready for production, he explains.

A true ASIC is a fixed piece of hardware that is quite fast and optimized for a specific task, Scalera explains. It can not be reprogrammed on the fly, he adds.

However, times are changing and the expanding gate counts of FPGAs and their reconfigurability is making the devices more price-competitive over the long haul.

ASICs are excellent devices with a performance edge over FPGAs, but when it comes time upgrade or reconfigure your system, you have to do the ASIC all over again, which is becoming more expensive every year, says Dennis Kish, vice president of marketing at Actel in Sunnyvale, Calif.

The cost of upgrading an ASIC today has gone up by an order of magnitude, he says. The cost of producing a new ASIC mask can be anywhere from $1 to $2 million, Kish adds.

For example if an ASIC goes bad and is sent back to the fabrication facility to be fixed, the entire process would take at least nine months, Scalera says.

If you have to change a circuit on an old design, just the cost of the verification process alone may be enough to kill the entire program, Kish says. The reconfigurability aspect of FPGAs and their expanding gate counts make them an excellent solution for that type of obsolescence problem, he adds.

"FPGA gate counts are expanding faster than Moore's law," says Henk Spaanenburg, senior defense technologist at Mercury Computer Systems in Chelmsford, Mass. This capability will enable FPGAs to have the performance of 10 general-purpose processors in one device, he adds.

Some FPGAs may use cores based on PowerPC or DSP chips, enabling multiprocessing systems to be placed one board, Spaanenburg says. Those processors have limits on the number of bits they might be able to do, but with an FPGA there is no limit, he adds.

When adaptive computing is performed through FPGAs, flexibility is at a premium, Spaanenburg says. For example, a FPGA may have multiple personalities programmed on it, he continues, then dynamically reconfigure based on the different protocols coming in.

Mercury engineers are working with experts at Annapolis Micro Systems in Annapolis, Md., to combine their race and signal processing expertise with Annapolis's reconfigurable WildFire FPGA-based single-board computers.

With FPGAs you can create a multiprocessing system not just on a board but on a chip, says Jane Donaldson, president of Annapolis Micro Systems. Annapolis will not undertake a design unless it will have 10 times the performance of a normal DSP application, she says.

Having programmable logic in hardware enables Annapolis's 130 MHz WildFire boards to have the same output as a 1-gigahertz multiprocessing system, she says. Annapolis engineers use Xilinx FPGAS for their boards, Donaldson adds.

Embedded FPGA designers

The embedded FPGA market is growing rapidly, with companies every few months coming out with new ways to put more and more functionality onto FPGAs through IP cores. The competition is tight, with each one promising more gates than the other as well as software that provides easy reconfigurability.

The QuickDSP family of FPGAs from QuickLogic enables designers to offload standard DSP tasks, such as FFTs onto an FPGA.
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Engineers at Xilinx, one of the first companies to really take advantage this market, expanded their FPGA product line late last year with the release of their Platform FPGA initiative. The first product of the initiative will be the Xilinx Virtex-II FPGA, Xilinx officials say.

The Platform FPGA is a solution that integrates a variety of hard and soft IP cores on a single device whose hardware and firmware can be upgraded at any time, Xilinx officials say. The programmability of the architecture reduces system development time yet enables a single Platform FPGA to be targeted for multiple applications. This programmability also enables designers to optimize systems throughout the development cycle and offers co-design flexibility for trading-off hardware and software design implementations, company officials say.

Platform FPGAs provide embedded processors for system control, DSP cores for customized data filtering and parallel processing to maximize bandwidth, and 3.125 gigabit serial and high bandwidth source-synchronous I/O ports for high-speed data communication throughout the system, Xilinx officials say.

Under the initiative Xilinx allied with IBM, Mentor Graphics, Synopsys, Wind River Systems, and The MathWorks.

Engineers at QuickLogic in Sunnyvale, Calif., are placing more functionality on their FPGAs by embedding DSP cores on the chips, says Jon Ewald, QuickLogic product marketing director. The tasks that a DSP usually does over and over again such as FFTs can now be offloaded onto an FPGA, so the processor can focus on housekeeping functions, Ewald explains.

Another advantage is that the FPGA can be reprogrammed on the fly, Ewald says. For example you simply change a coefficient or use the software to tell the hardware what to do once every clock cycle, he adds.

QuickLogic's DSP products, the QuickDSP family, offer fast and easy implementation for high-performance communications applications, including those for wireless and digital subscriber lines, QuickLogic officials claim. In addition, it offers as many as 662,208 system gates of logic and as many as 82,900 RAM dual-port SRAM bits. QuickLogic also recently released a full hardware/software support system for the product, company officials say.

Actel, traditionally a supplier of one-time programmable FPGAs, recently entered the reprogrammable market with their VariCore EPGA, or embedded programmable gate array. EPGAs are IP cores for ASIC and application specific standard product (ASSP) systems on a chip (SoCs).

Actel formed the VariCore business unit early last summer to develop its EPGA cores. The new unit benefited from technology acquired from Prosys Technology and GateField Corp., which Actel purchased last year, Actel officials say.

VariCore EPGA blocks are "soft hardware" core tiles, based on a three-input look-up-table, Actel officials say. Primary embedded gates (PEGs), consisting of 2,500 ASIC gates, are the blocks of EPGAs. These PEG blocks are scaleable and configurable in the VariCore product line. The blocks have been designed in 0.18um CMOS SRAM technology.

"Beyond the benefits of time to market and reduced design risk, most of today's SoC designers think some form of reconfigurability is necessary or desirable for the success of their design application," says Yankin Tanurhan, director of embedded FPGA at Actel. "Adding reconfigurability to SoC designs is vital in simplifying adaptation to changing standards, both during development and in post deployment. [Another critical part of] SoC designs is to gain flexibility necessary for creating multiple products from a single SoC device."

Honeywell Space Systems experts in Clearwater, Fla., are also looking at a RAM-based FPGAs for their space applications.

Honeywell officials believe "that reconfigurable computing will become very important for processing onboard satellites," says Richard Elmhurst, business development manager at Honeywell Space Systems. "Our plan is to offer products at the processing board and subsystem level for use on board satellites for both payload data and control processing.

"The main advancements we are designing into our reconfigurable products are non-upsettable hardware and easy-to-use systems software," Elmhurst continues. "We are designing and fabricating radiation-hardened versions of COTS-interchangeable, RAM-reconfigurable FPGA components for use in board and subsystem applications where single-event-upset of configuration memories or active routing elements is undesirable.

"We are also developing companion software development tools and real-time operating system support such that our onboard reconfigurable processing will be as easy to use as are general purpose software programmable processors," he adds.

While many commercial FPGA manufacturers are placing millions of more gates on their FPGAs, the space industry will move a little slower to embrace them, Elmhurst says. Devices with such high gate counts are not reliable enough for space, he explains. There is too much radiation in an on-orbit platform, Elmhurst notes.

The DARPA ACS program

One of the driving forces behind adaptive computing technology is the Defense Advanced Research Projects Agency (DARPA) in Washington, D.C. The U.S. Department of Defense agency initiated a program in the late 1990s called Adaptive Computing Systems (ACS), aimed at creating "unprecedented capabilities for dynamic adaptation of information systems to threats and rapidly evolving mission requirements of the Department of Defense, according to the DARPA Information Technology Office's (ITO) Internet site.

Organizations working under the ACS program will "develop the COTS hardware components, design, programming, and runtime environments to enable an application to reach through to the hardware layer and directly manipulate the datapath-level architecture at runtime to optimize the application-level performance," the ITO's site states. The program's goal is to "enable the rapid realization of algorithm specific hardware architectures on a low-cost COTS technology," according to the site.

Three companies that successfully performed work under DARPA ACS program were Annapolis Micro Systems, BAE Systems, and Xilinx.

For their part in the DARPA ACS program Annapolis Micro Systems engineers focused on target recognition, Annapolis's Donaldson says. They built a WildStar FPGA board that had the capability of 52 PowerPC 740 boards running at 400 megahertz, she claims.

It is done with a huge amount of parallelism in the FPGAs, doing the same tasks over and over again, Donaldson explains. It is also reprogrammable, she continues, you can download the instructions directly to the chips.

By placing all that processing capability on one FPGA-based board, Annapolis engineers were able to reduce space, weight, power, and cost, Donaldson says.

The WildFire board also mitigates obsolescence issues because it is reprogrammable, says Pat Stover, vice president of sales at Annapolis. "You don't have to reinvent the wheel," he continues, just run an algorithm replacement to reconfigure the hardware.

Annapolis's DARPA work was performed for the U.S. army Night Vision Laboratory at Fort Belvoir, Va., Donaldson says.

BAE Systems was contracted by DARPA when they were still Sanders to develop a new, more powerful computing system with reconfigurable modules. The system had to be able to process certain classes of signal processing algorithms with as many as 100 times the power of the best of today's microprocessor-based systems.

Under the contract BAE Systems engineers developed and demonstrated a context switching reconfigurable computing (CSRC) system that performs multiple computations simultaneously at very high speeds.

BAE systems experts custom-designed a chip from the ground up with more than 10 million transistors, says Steve Scalera, CSRC program manager at BAE Systems. The goal was to be able to reconfigure the FPGA in real time, Scalera says. BAE Systems engineers were able to get the reconfiguration time down to 100 milliseconds at first, he notes.

However, that was not fast enough for an electronic warfare application, Scalera continues. If you are in an aircraft with a missile coming at you, 100 milliseconds will not cut it, Scalera says. BAE Systems engineers had to go to dynamic nanosecond-reconfigurability to achieve their real-time goals, he explains.

A millisecond is one thousandth of a second, a microsecond is one millionth of a millisecond, and a nanosecond is a thousand times faster than a microsecond.

A basic microprocessor chip is not reconfigurable, but relies instead on fixed hardware logic controlled by instruction decode logic, BAE Systems officials say. One of the new modules will have a number of reconfigurable "logic" configurations, compute elements similar to mini-programs, stored in multiple layers on the device itself.

The configuration of a CSRC device's logic is controlled according to algorithms mapped into the logic and based on data set requirements, BAE systems officials say. Through a method known as "context switching," all of the system's logic is targeted to the currently active portion of the algorithm. By continuously using all of the logic, a CSRC module increases performance but also maintains full programmability. This approach avoids the cost and size constraints normally encountered when transistor counts are increased and integrated circuit geometries are reduced to enhance performance, BAE Systems officials claim.

The context switching feature also enables data to be retained when the FPGA is reconfigured, Scalera says. Before this technique, any prior data was wiped out when the chip was reconfigured, he explains.

The CSRC demonstrations showed how context switching hardware improves performance in computing domains, such as mathematical computations, image manipulation, and adaptive computing. The BAE Systems team also demonstrated three applications — automatic target recognition, SAR, and 3D image manipulation for the DARPA contract.

As a result of their success BAE Systems engineers have won a follow-on contract with DARPA called DRACS or Dynamic Reconfigurable Adaptive Computing Systems, Scalera says.

DARPA officials have tasked Xilinx experts to design a suite of software tools for creating applications that can reconfigure FPGA-based hardware during runtime when a deployed system is operating. Xilinx is working with Virginia Polytechnic Institute in Blacksburg, Va., on the project.

The foundation for the tools will be the Xilinx JBits application programming interface (API), which Xilinx created to help designers build systems that can be upgraded after installation at a customer's premises. The JBits API is implemented in the Java programming language and enables software to directly access all of the configurable elements in Xilinx FPGAs.

"Our goal is to use an approach such as the JBits API for direct compilation and configuration of FPGAs in systems," Xilinx's Guccione says. "We believe it's possible to use this enabling technology to build a complete set of tools that will provide an environment similar to that available for modern software development systems. The tools and supporting libraries will interact with each other and permit the creation of reconfigurable applications from a fast, friendly and integrated suite of software.

"We chose Java because we like the language," Guccione says. It is an organized language with strong debugging tools, he adds.

"In addition to the obvious benefits this technology offers for defense and space-based systems, this development program clearly supports the defense industry's initiative to use commercial off-the-shelf, or COTS, technology," says Rick Padovani, director of the Xilinx Defense and Aerospace Group. "All Xilinx FPGAs as well as the Java-based development tools are COTS products. This parallels a continuing trend to choose off-the-shelf FPGAs over custom products such as ASICs."

The technology presently has about 100 users and is being looked at for compute-intensive applications such as encryption implementation, Guccione says.

The fast and flexible Xilinx JBits API enables applications designers to specify in Java code all details about FPGA routing and logic resources. The primary goal of the Xilinx research and development effort will be to raise the level abstraction so that reconfigurable FPGA designs can be completed by a wider range of developers, including software programmers, Xilinx officials say.

Components of the tool suite include a board interface API, a library of macrocells or cores, written in Java, whose parameters can be set at runtime within the application, an interactive debug tool, and a FPGA device simulator. Runtime parameter-driven cores will raise the level of abstraction for designers, relieving them of the need to have exacting knowledge of FPGA resources, Xilinx officials say.

Xilinx's partners on the program include Annapolis Micro Systems, Mirotech Systems, in St. Laurent, Quebec, and Virtual Computer Corp. in Reseda, Calif.

User-friendly FPGAs

Now that the performance advantages of FPGAs are being realized, the next step in reconfigurable computing will be to eliminate the need for digital designers and have C programmers be able to program FPGAs as easily as they write code today, Donaldson says. At this time it is very difficult to program in hardware.

Tools need to be created to give the FPGA designers the same ease that compilers and other mechanisms give to software programmers, she explains. Annapolis engineers are working on tools right now that should be a big step toward that goal, Donaldson says. However, she declined to go into specifics at this time.

It can be frustrating for people used to the ease of programming CPUs, but it should be noted that CPUs have about a thirty year head start on FPGAs, Donaldson says. However FPGAs are catching up at a nice pace, she adds.

Celoxica, Wind River, and Xilinx partner to ease application design in hardware

Engineers at Celoxica Limited in Abingdon, England, Wind River Systems in Alameda, Calif., and Xilinx in San Jose, Calif., have joined hands to create a suite of tools that enables system designers to quickly reconfigure their hardware from any location worldwide.

The partnership enables Celoxica's products for rapidly designing applications in reconfigurable hardware to be interoperable with Xilinx field programmable gate arrays (FPGAs) and Wind River's VxWorks real-time operating system (RTOS).

The joint venture is built on an initiative between the three companies to demonstrate Internet Reconfigurable Logic (IRL). IRL makes it easy for network upgradeability of hardware, says Wallace Westfeldt, marketing manager for IRL Solutions at Xilinx. Users will be able to download upgrades to their FPGAs right off their network Intranet, he says.

For example, an operator at a remote satellite bay station, who would otherwise have to wait weeks for a hardware engineer to get to him, can now upgrade his hardware in minutes, Westfeldt says.

The IRL technology gives Xilinx customers the ability to control their product life cycle and it alleviates the pressure on designers to get products to market quicker and with optimum performance, he explains.

"Celoxica's aim is to radically shorten the process of designing new applications in hardware," says Mat Newman, senior vice president of corporate development at Celoxica. "Our system-level approach addresses critical customer concerns by overcoming the design inefficiencies and financial overheads that make predicting and exploiting new market opportunities a gamble.

"Wind Rivers' market-share leading VxWorks RTOS with Celoxica's strength in IRL and Xilinx's leading FPGAs gives our mutual customers a pre-integrated, cutting-edge hardware-software solution that gets them to market faster," Newman adds.

The technology will directly help military users of image processing systems, head-up displays, radar, and sonar, says Selwyn Petterson, account director for military and aerospace market at Celoxica.

The agreement will help out Wind River's embedded customers, because they will be able to reconfigure their hardware quickly and with the robust environment of a real-time operating system, says Gareth Noyes, product marketing manager for certification at Wind River. "Our aim is to provide a total balanced system between CPUs and FPGAs."

The easy upgradeability of FPGAs will also enable Wind River's customers to battle obsolescence, Noyes says.

Celoxica's DK1 is a C-to-hardware design suite for the rapid expression and conversion of software algorithms into hardware implementations on FPGAs. It also enables system designers and software developers to accelerate algorithms by expressing them in parallel and mapping them directly to hardware without a hardware description language, better known as HDL, step.

When training people in VHDL (VHSIC Hardware Description Language) it would take 18 months to begin to see expertise, now with DK1 they can learn in three days, says Will Goalby, vice president of communications at Celoxica. The DK1 design suite cuts design-times to weeks and days, he adds.

With DK1 engineers use Handel-C, a high-level language based on ANSI-C, to write complex algorithms targeted for migration to hardware. A C-programmer can learn Handel-C in a matter of days. DK1 provides migration from a C-like code, with extensions for parallelism and timing, directly to hardware. As a result, space and time issues can be controlled in C and hardware design is no longer limited to hardware design experts, but accessible to application specialists, including system architects and software engineers, Celoxica officials say.

Wind River engineers intend to offer development tools and runtime support to speed designs of systems containing FPGAs. This extension to Wind River

The extension will enable system designers to choose from a suite of Wind River products to profile bottlenecks and CPU time-intensive tasks in software, and then migrate these sections of code where appropriate into hardware.

The technology involves a new language interface created by Xilinx engineers to enable their IRL technology in a VxWorks environment. They designed the PAVE (VxWorks environment) interface as an extension to the VxWorks RTOS application programming interface (API) which enables the developer to reconfigure FPGAs after deployment.

The PAVE technology enables developers to create hardware upgradable embedded systems using the Wind River Tornado integrated development environment, VxWorks RTOS, and Xilinx programmable logic devices.

"Partnering with Wind River helps our customers more quickly develop field upgradable applications using tools familiar to systems designers," says Rich Sevcik, senior vice president of IP, support, and software at Xilinx. "In developing Xilinx Online applications, users can realize a savings in their overhead and field engineering costs once the applications are employed." — J.M.

Who's Who in reconfigurable computing

Actel, Sunnyvale, Calif., 408-739-1010,
Altera, San Jose, Calif., 408-544-7000,
Annapolis Micro Systems, Annapolis, Md., 410-841-2514,
Atmel, San Jose, Calif., 408-441-0311,
BAE Systems, Nashua, N.H., 603-885-4321,
Celoxica, Abingdon, England, 44 (0) 1235 863656,
Honeywell Space Systems, Clearwater, Fla., 727-539-4611,
Mercury Computer Systems, Chelmsford, Mass., 978-256-1300, http:///
QuickLogic, Sunnyvale, Calif., 408-990-4000,
Silicore, Minneapolis, Minn., 612-722-3815,
Sky Computers, Chelmsford, Mass., 978-250-1920,
Wind River Systems, Alameda, Calif., 510-748-4100,
Xilinx, San Jose, Calif., 408-559-7778,

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