RapidIO: A high-performance network for future military processing systems

Military computers of the future will have to be much faster than they are today to perform computationally intensive algorithms such as real-time hyperspectral imaging or space-time Adaptive Processing (STAP).

Apr 1st, 2002

by Warren Rosen, John Adams, and Vaughn Adams

Military computers of the future will have to be much faster than they are today to perform computationally intensive algorithms such as real-time hyperspectral imaging or space-time Adaptive Processing (STAP). One large step toward increasing computer throughput may involve a new switched-network fabric called RapidIO.

A typical hyperspectral imager can generate in excess of 600 megabits per second of data. Computers usually convert the data from encoded radiance to reflectance, correct the data for atmospheric, sensor, and deep-shadow effects, and then perform a K-L transform. Only by speeding network capacity and latency by an order of magnitude over today's computers can systems designers support the processing and data transfer loads that technologies such as hyperspectral imagers generate. At the same time, designers will place an increasing reliance on commercial off-the-shelf (COTS) technology to control costs and decrease insertion time.

While newly emerging standards such as HyperTransport, InfiniBand, Arapahoe/3GIO, and RapidIO offer the promise of high speed and low latency for high-performance embedded and parallel processing, RapidIO is an attractive choice for military applications for several reasons.

History of RapidIO
RapidIO is a set of standards of the RapidIO Trade Association. Standards committees have defined serial and parallel implementations, an interoperability specification, and logical layers supporting shared memory and message-passing processing paradigms. The parallel physical layer standard became public in March 2001. The standard defines a high-speed, low-latency packet-switched interconnect technology designed for processor-to-processor, processor-to-memory, and processor-to-peripheral interconnects. The basic interconnect is a bi-directional link that uses switches to form simple or multistage switched topologies and meshes.

The parallel specification defines unidirectional link data rates of 4, 8, or 16 gigabits per second, with 4- and 8-gigabit-per-second components promised in the near future. It operates at distances as far apart as 30 inches over standard printed circuit board materials using 8- or 16-bit-wide bi-directional links that use low-voltage differential signaling (LVDS) for low-power, high-speed operation.

The serial specification defines data rates of 1, 2, and 2.5 gigabits per second; integrators may gang 4 serial links together for an aggregate data rate of 2, 8, or 10 gigabits per second. It operates at distances as far apart as 10 meters with slightly higher latency.

The RapidIO packet features an efficient header and variable payload sizes as large as 256 bytes. Four-byte control symbols transmit status and control information between the devices on either side of the link. They transmit information such as acknowledgments, free buffer space, packet spacing requests, and error information. The address space is flat and supports as many as 65,000 nodes. The architecture supports all necessary microprocessor and I/O transactions including support for shared memory, and is transparent to existing applications and operating system software.

With the exception of only a few requirements such as radiation hardening, the requirements for a high-performance network in military applications are largely the same as in the commercial world-performance in terms of scalability, security, determinism, reliability, physical requirements such as power consumption and footprint, cost, and risk. Military applications, however, may impose more stringent requirements than do commercial applications. The real-time performance in an avionics environment, for example, may be measured in a few milliseconds. Fault tolerance and security, in addition, are key issues.

RapidIO defines performance in terms of throughput and latency. The link bandwidth and the efficiency of the protocol determines throughput. The link bandwidth (or at least the bandwidth-distance product) of all the network protocols is likely to be about the same and limited by the capabilities of CMOS I/O pads and the number of pads that can be placed on a chip.

The protocol, on the other hand, largely determines latency. RapidIO has several features that contribute to low latency, including small packet size, efficient header, and the ability to embed control packets within the data stream. Furthermore, RapidIO's creators intended it from the outset to interface directly to the processor bus; this eliminates the latency associated with I/O interfaces such as PCI.

Architectural advantages
In the near future processors such as the Motorola 8540 will be available with an onboard RapidIO interface to improve performance and reduce chip count and cost. These features result in very low latency. Simulations indicate that a 192-node network, for example, can perform a 64-bit remote read in about 400 nanoseconds, measured from the time the network sends its request to the physical layer to the time it receives the response from the physical layer of the source node.

These results compare favorably to the best customized proprietary networks. The ability to embed control symbols within data packets was found to improve latency by about 1 percent in lightly loaded networks and delayed the onset of saturation by about 5 percent.

Scalability is an important requirement as the complexity of military signal-processing algorithms grows. For example, the complexity of the STAP algorithm increases as the cube of the number of elements in the system. Scalability is defined with respect to the attributes of the system such as bandwidth, latency, or quality of service. Bandwidth and latency are critical.

Security is a requirement that is not an issue for most commercial signal-processing systems but is critical for military systems. Military systems refer to security not so much as resistance to outside attack but rather to the ability of the system to prevent secure information from reaching unauthorized segments of the system itself. Ideally, performance dictates that this functionality should come in hardware rather than software. Unfortunately none of the protocols mentioned provides the necessary hooks for hardware-level security, primarily because it is not an issue in most commercial systems and this problem must be addressed by any military system integrator.

Determinism is an important issue for real-time systems. Jitter is a large variability in how long it takes a message to get through. The presence of jitter requires designers to use the worst case in scheduling. A network with little jitter can be scheduled more heavily than one that has a lot of variability.

The RapidIO specification does not explicitly define deterministic networks but it has features that enable vendors to build them and still conform to the standard.

Reliability issues
Reliability is an obvious requirement for military systems and RapidIO provides several useful hooks supporting fault tolerance and error recovery. The protocol is designed to recover from all single-bit errors and most multi-bit errors with no software or higher-level system intervention. In addition it can detect and notify software in the event of more severe errors in order to redirect traffic around failed devices for high-reliability applications.

The physical environment for military systems ranges from harsh to extremely harsh. At the same time, power and space are often at a premium. RapidIO is an extremely lightweight protocol that designers can realize in a relatively small number of gates. This means that power consumption is low and the footprint small. In fact an entire interface can fit on a modest field programmable gate array (FPGA) with space for added functionality.

Support for RapidIO
RapidIO has strong commercial support; the trade association comprises 47 major chip developers, system OEMs, and test equipment manufacturers. Furthermore the members of the trade association are working hard to assure commercial success and reduce risk by providing bus functional models, synthesizeable cores, and an interoperability platform. Scientists currently are testing prototypes for all major components in the laboratory and a variety of switches and bridges will be available in the near future. An 8-bit physical layer core is available from one FPGA vendor.

Finally, the high throughput and efficient header make RapidIO appropriate for interconnects beyond the processors. In a small platform, such as an avionics system, it might make sense to implement the links from the sensors to the processors and from the processors to the displays using serial RapidIO interfaces, and the links within the boxes using the parallel version. This would result in an efficient, seamless architecture with a flat address space. In less latency-sensitive applications it would also allow the distribution of processing elements throughout the aircraft for improved weight distribution and survivability and it would also reduce cost through the use of common interfaces.

The authors are with Rydal Research and Development Inc. in Rydal Pa. Contact them by phone at 215-886-5678, by e-mail at jadams@rydalresearch.com, or on the World Wide Web at http://www.rydalresearch.com/.

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