The new frontier: reconfigurable computing
Reconfigurable computers chips or systems that alter their personality to adapt to changing applications through the use of field programmable gate arrays (FPGAs) are receiving growing attention.
Reconfigurable computers — chips or systems that alter their personality to adapt to changing applications through the use of field programmable gate arrays (FPGAs) — are receiving growing attention. The improved performance of FPGAs, and especially of the software tools that help program them, are giving designers technology able to reconfigure itself on the fly to improve performance and stave off obsolescence.
By John McHale
Military designers are looking to new reconfigurable computing architectures not only for dramatic improvements in performance, but also as a way to update system capabilities quickly without costly wholesale replacement of hardware and software. This new breed of reconfigurable computing, which is based on field programmable gate arrays (FPGAs), is of particular interest to those who design computationally intensive processors for radar, sonar, target recognition, terrain mapping, and image processing.
Reconfigurable computing systems, which can reconfigure their circuits during operation to adapt to new tasks or failed components, promise to be 100 to 1,000 times faster than microprocessor-based systems that are prevalent today. Yet much more work needs to be done before reconfigurable computing becomes a standard piece of processing equipment.
While the performance advantages of FPGAs are formidable the devices are still not widespread in military signal processing applications. Reconfigurable computing, however, is gaining in popularity because of the growing number of software development tools that are becoming available for FPGAs. These tools cut down production time and costs and make it more cost-effective for designers to take advantage of the high-performance and obsolescence-mitigating characteristics of reconfigurable computing.
FPGAs enable designers to create multiprocessing systems on chips as well as on boards, says Jane Donaldson, president of Annapolis Micro Systems, an adaptive computing specialist in Annapolis, Md. Annapolis engineers will not undertake a design unless it promises to offer at least 10 times the performance of a normal DSP application, she says. For their adaptive computer boards, Annapolis engineers FPGAS from Xilinx Inc. of San Jose, Calif., she adds.
Programmable hardware gives the Annapolis 130 MHz WildFire board the same output as a 1-gigahertz multiprocessing system, Donaldson says. About three years ago, for example, Annapolis engineers replaced 52 PowerPC 740 boards with one of their WildStar FPGA boards running at 400 megahertz. The work, Donaldson says, was part of the Defense Advanced Research Projects Agency's (DARPA) Adaptive Computing Systems program performed for the U.S. Army Night Vision Laboratory at Fort Belvoir, Va.
Annapolis engineers use a huge amount of parallelism in the FPGAs, which does the same tasks over and over again, Donaldson explains. Its reprogrammability not only enables designers to download instructions directly to the chips, but also mitigates obsolescence, says Pat Stover, vice president of sales at Annapolis. "You don't have to reinvent the wheel," he continues. Designers simply run an algorithm replacement to reconfigure the hardware.
The technology represents another step in the evolution from sequential processing to parallel processing, he adds. Sequential processing performs tasks in a specific order, one after another. The Intel Pentium, AMD K-62, and Motorola Power PC microprocessors are examples of this. Parallel processors, on the other hand, perform tasks concurrently.
Change on the fly
Reconfigurable computers can morph their personalities based on the tasks at hand, whether it is performing Fast Fourier Transforms (FFTs), handling interrupts, or even reconfiguring radar or sonar sensors based on changing mission parameters. Designers of these systems will be able to place the capability of a large multiprocessing system onto small FPGAs, which will process signals in parallel.
The key to unlocking the adaptive powers of FPGAs lies in what experts call "soft hardware," explains Ray Alderman, executive director of the VME International Trade Association in Scottsdale, Ariz. Essentially, soft hardware enables an FPGA architecture to mimic the nature of another computer. Engineers do this first by using a hardware description language, such as the VHSIC Hardware Description Language (VHDL), to capture the functionality of a computer.
This description of the computer's functionality is called an intellectual property (IP) core. Engineers then program that IP core into the FPGA architecture. The beauty of this process is its ability to perform the functions of one computer in a smaller space and with greater performance in an FPGA architecture, Alderman explains. These new kinds of reprogrammable computers are relatively easy to upgrade and reconfigure because their functions program into the hardware on the fly, Alderman adds.
The primary obstacle confronting widespread use of reconfigurable computing involves the often-tedious process or programming FPGAs in VHCL, which is difficult and time-consuming, says Bob Donaldson, director of engineering at Annapolis. Programming can sometimes take anywhere from a few months to a year depending on the application, which can be very costly, he adds.
Now that systems designers are starting to realize the performance advantages of FPGAs, the next step in reconfigurable computing will be to eliminate the need for digital designers; instead, C software programmers will be able to program FPGAs as easily as they write code today, Jane Donaldson says. The performance advantages, she says, will be tremendous. Jane Donaldson says she remembers her company's project to replace 52 PowerPC boards with one of Annapolis's FPGA boards; it took nine months.
To combat that problem, engineers at Annapolis and Celoxica in Abingdon, England, offer development tools that ease programming in hardware. Annapolis experts recently released their CoreFire design suite and Celoxica released their DK1.1 product.
CoreFire enables the user to implement algorithms quickly on FPGA-based high-speed processing boards, Bob Donaldson says. The CoreFire Design Suite is a graphical user interface tool that uses data flow methodology. This approach combines Annapolis's extensive systems and application development experience with their large collection of high-performance IP cores, he says.
"Before CoreFire, 'ease of use' and 'FPGA programming' were incompatible notions," Jane Donaldson claims. "With CoreFire it is possible to completely implement an algorithm on our Wild-family FPGA boards without ever descending to the lower level hardware details, saving months of development time and money."
The Annapolis tool can automatically and quickly provide reconfigurable designs for new FPGA boards that will have as many as 30 million gates. Jane Donaldson says she believes that the CoreFire technology will "blow open the doors of the highly specialized FPGA design field, making this technology available to a much broader audience."
CoreFire's drag-and-drop, approach frees the designer from gate-level design minutia and helps him concentrate on the relatively abstract "data-flow" level of his problem. That way "he can concentrate on solving problems, not on designing hardware," Jane Donaldson says. Application developers no longer have to learn hardware-design methodologies, such as VHDL, Verilog, or low-level schematic entry, she adds.
These tools will eventually reduce development time from months to weeks, Bob Donaldson says.
Engineers at the Naval Research Laboratory (NRL) in Washington are working with CoreFire to develop FPGA solutions for electronic warfare. NRL experts, who are looking to shorten the design cycles that go with hand coding in VHDL, say they find the Annapolis CoreFire tool is a big help, says Tony Spesio, an engineer in electronic warfare support at NRL.
"CoreFire is a concept I view as revolutionary — making FPGAs more usable," Spesio says. NRL engineers are using CoreFire to help Annapolis engineers find possible problems the tool might face in different scenarios, Spesio says. "We bought the CoreFire license in October" and since then Annapolis has revised their tool successfully to deal with each problem NRL encountered, he explains.
FPGAs can provide much greater signal-processing throughput than can microprocessors, Spesio says. The one roadblock has been making them easier to use, but tools such as CoreFire are causing that roadblock to fall, he adds.
CoreFire runs on the Annapolis Wild family of FPGA boards, which use Xilinx Virtex, Virtex E, and VirtexII FPGAs. Currently, CoreFire only works with Annapolis FPGA boards, which use only Xilinx devices, Bob Donaldson says. Eventually, it will run with other FPGAs, he adds.
The CoreFire Design Suite includes the CoreFire Application Builder, the CoreFire Application Debugger, the CoreFire Module Libraries, and the CoreFire board support package libraries. Originally released with a library of cores geared toward signal processing applications, Annapolis's CoreFire engineering design team is also delivering libraries that support other application families such as image processing, stream processing, software radio, and text processing.
CoreFire also supports hierarchical designs, Donaldson says, in which designers can create their own core modules and libraries of cores built out of standard CoreFire components. The modular approach will make it easier to build and test the more complex FPGA applications, Annapolis officials say.
Engineers at Celoxica are introducing their DK1.1 tool and the next version of their Handel-C-to-hardware design suite, which they claim have made hardware design easier and more cost-effective. The new product reduces development cycles for hardware implementation on FPGAs, Celoxica officials say
DK1.1 provides migration from a C-like code, with extensions for parallelism and timing, directly to hardware. As a result, space and time issues can be controlled in C and hardware design is no longer limited to hardware design experts, but accessible to application specialists, including system architects and software engineers, company officials say. Meanwhile, Handel-C is a high-level language based on ANSI-C for writing complex algorithms for hardware, Celoxica officials say.
A C-programmer can learn Handel-C in a matter of days, while training people to write in VHDL would take about 18 months, says Will Goalby, vice president of communications at Celoxica. The design suite cuts design-times to weeks and days, he adds.
For example one company used a team of hardware engineers to hand code an FPGA application and it took them about 9 months and 200 pages of code, Goalby continues. However, with DK1.1 it took one engineer 2 months and only 40 pages of code, he says.
The DK1.1 design suite supports the design, validation, iterative refinement, and implementation of complex algorithms in hardware. It includes built-in design entry, simulation, and synthesis — all driven by Handel-C, Celoxica officials say.
DK1.1's platform independence separates it from competing products, says Hammad Hamid, a senior applications engineer at Celoxica. DK1.1 can work with any FPGA such as Actel, Altera, or Xilinx, he continues, and is not locked into a proprietary design, Hamid explains.
DK1.1 includes features for system-level hardware/software co-design, co-simulation support for ARM and PowerPC embedded processors, improved synthesis, enhanced area and delay analysis, improved VHDL output, Verilog output, 100 times faster simulation, and support for Actel, Altera Excalibur, and Xilinx Virtex II Pro devices.
The simplicity of Handel-C and other Celoxica technologies "make it easier to achieve an optimal design partitioning between embedded processors and programmable gates," says Rich Sevcik, senior vice president of the FPGA Products Group at Xilinx. "These products will support Virtex-II Pro designers by providing a unique tool for fully exploiting the potential of Platform FPGAs."
The combination of increased gate count and the tools such as DK 1.1 available to develop FPGA solutions is helping reconfigurable computing solutions expand their presence in space and satellite applications, says Howard Bogrow, marketing manager for aerospace and defense at Xilinx.
"Our products are getting designed into a lot of applications in the space market," Bogrow continues. This has not been a traditional market for reprogrammable SRAM technology, however, satellites and the electronics used in satellites such as cameras involve a lot of data processing, which FPGAs can provide, he explains.
DK1.1 enables reprogrammable system-on-a-chip designers to make informed critical decisions about hardware/software partitioning, Celoxica officials say. With the new mixed-language facility users can call C/C++ functions from Handel-C descriptions and Handel-C functions from C/C++ programs.
Apart from allowing designers to explore different partitioning schemes using a "what-if" scenario, software functionality can now convert to hardware iteratively. The mixed-language approach also allows hardware designers to use C/C++ test benches to verify Handel-C designs.
The DARPA ACS program
One of the driving forces behind adaptive computing technology was the Defense Advanced Research Projects Agency (DARPA) in Arlington, Va. The U.S. Department of Defense agency initiated a program in the late 1990s called Adaptive Computing Systems (ACS), aimed at creating "unprecedented capabilities for dynamic adaptation of information systems to threats and rapidly evolving mission requirements of the Department of Defense, according to the DARPA Information Technology Office's (ITO) Internet site.
The ACS program developed new approaches to the design of computer hardware that incorporates dynamic configuration capabilities, DARPA officials say. The resultant devices enable the DOD to develop a wide variety of specialized systems by reusing a relatively small set of hardware designs, each of which can be affordably produced in high volumes, DARPA officials say. The program was officially wrapped earlier this year, DARPA officials say.
FPGA-based reconfigurable computing systems developed under ACS are currently being looked at for use in target-aided recognition in a tank application, by the U.S. Navy in Aegis cruisers, various radar programs and the Global Hawk unmanned aerial vehicle, says Bob Reuss, ACS program manager at DARPA. FPGA-based systems significantly reduced size and weight, while greatly increasing performance in many signal processing applications, he adds.
Accomplishments of the ACS program included: a demonstration of 100x to 1000x reduction in compilation time for ACS implementations; ACS defense system insertion for high dimensionality sonar beamforming, synthetic aperture radar, signal processing, and automatic target recognition; defining high-level and low-level optimization approaches to implement application specific integrated circuit (ASICs); and defining the appropriate levels of customization that provide the greatest performance benefit for digital signal processor (DSP) intensive ASIC-based systems such as wide band adaptive radar receivers and infrared image processing, Reuss says.
Actel releases one million gate Flash FPGA
Officials at Actel Corp. in Sunnyvale, Calif., earlier this year launched their first one-million gate Flash field programmable gate array (FPGA), the ProASIC Plus. The new second-generation FPGA family, based on a 0.22-micron process, will consist of six devices ranging in density from 150,000 to 1 million system gates.
The combination of a fine-grained, application-specific integrated circuit (ASIC)-like architecture and non-volatile flash configuration memory makes the new Actel device a strong application-specific integrated circuit (ASIC) alternative, Actel officials say.
The devices are live at power up, secure, and require no separate configuration memory, all characteristics shared by ASICs, company officials say. The ProASIC Plus architecture supports popular ASIC tool flows, reducing time to market and permitting designers to migrate easily between FPGA and ASIC solutions, Actel officials claim.
ProASIC Plus devices are as fast as 100 MHz and enable designers to interface between 3.3- and 2.5-volt devices in a mixed-voltage environment, Xilinx officials say. The ProASIC Plus family contains two advanced clock-conditioning blocks, each consisting of a PLL core, delay lines, and clock multiplier/dividers. Additionally, two high-speed LVPECL differential input pairs accommodate clock or data inputs. In-system programmability is supported through the IEEE standard 1149.1 JTAG interface, company officials say.
Supporting the ProASIC Plus family is Actel's Designer software, which includes place-and-route, timing analysis, and memory generation functionality, Xilinx officials say. Targeting ASIC and FPGA environments, the devices are also supported by third-party design tools from Cadence, Exemplar, Model Technology, Synopsys, and Synplicity. Because the ProASIC Plus devices work equally well with ASIC and FPGA design methodologies, designers can create high-density systems using existing tools and flows, Xilinx officials say.
Actel's ProASIC Plus devices offer levels of design security beyond SRAM-based FPGAs and conventional ASIC solutions, enabling an entirely new business model for intellectual property providers, company officials say. ProASIC Plus FPGAs are user programmed with a multi-bit key that blocks external attempts to read or alter the configuration settings, Xilinx officials say. Decapping and stripping of the ProASIC Plus device reveals only the structure of the flash cell, not the contents. Actel also offers a low-risk, cost-effective conversion path from Actel's non-volatile, single-chip ProASIC Plus FPGAs to ASICs when volumes warrant it, company officials say. The ASIC-like architecture and design methodology facilitate ASIC migration, minimizing time to market, system cost and the risks typically associated with conversions, Actel officials say.
Xilinx introduces Virtex-II pro FPGA
The Virtex-II Pro field programmable gate array (FPGA) from Xilinx Inc. of San Jose, Calif., integrates IBM PowerPC processors in the FPGA fabric with multi-gigabit serial transceivers to solve high-performance architectural challenges.
Xilinx engineers use the company's IP Immersion technology to integrate the Virtex-II Pro's two main requirements for next-generation systems — RISC processing and high-speed serial technology, Xilinx officials say. The FPGA fabric also includes active interconnect, blockRAM, and clock management features. The level of integration offers systems designers a high level of performance with low system cost, company officials say.
The Virtex-II Pro family "shifts the usage model for programmable technology from logic to systems," says Wim Roelandts, Xilinx president and chief executive officer. " With new Virtex-II Pro FPGAs, system designers can leverage the advantages of programmability at the architectural level. Virtex-II Pro family represents the fruition of decades of experience in microprocessor from IBM, high-speed serial from Conexant, development tools from Wind River, and our programmable logic technologies."
Xilinx partnered with leaders in each of these areas to deliver the product, he adds.
"Because we had access in advance to the preliminary information for the Xilinx Virtex-II Pro FPGAs, we were able to evaluate the architecture for our needs," says Stefano Gastaldello, optical multiservice networks/ASICs lab manager for Alcatel in Italy. "We've verified and are encouraged that it matches very well with the architecture of our next generation of high capacity optical multiservice nodes and gateways."
The Virtex-II Pro family supports as many as four PowerPC 405 processor cores each running as fast as 300 MHz, Xilinx officials say. The Xilinx immersion method enables hard IP cores to be diffused at any coordinate within the Virtex fabric while maintaining smooth integration with the surrounding array. IP Immersion technology intimately couples all of the high-speed buses on the core directly to the programmable fabric giving significantly higher system-level performance than an equivalent discrete processor, company officials claim.
Virtex-II Pro FPGAs also feature RocketIO technology, which is a multi-port, 3.125-gigabit-per-second serial interface available for Gigabit Ethernet, 10 Gigabit Ethernet, 3GIO, SerialATA, Infiniband, and Fibrechannel, company officials say. System designers have one platform that delivers emerging connectivity standards and allows them to increase their I/O performance, Xilinx officials say.
Software development, hardware development, and system integration solutions include compilers and integrated development environments from Wind River and GNU, Xilinx officials say.
Bittware designs reconfigurable PMC
Engineers at BittWare, Inc., in Concord, N.H., recently designed a reconfigurable PMC that is based on the Xilinx Virtex-II field programmable gate array (FPGA). The card merges FPGA technology with the Analog Devices ADSP-21160 SHARC digital signal processor (DSP).
The Reef-PMC+ board lets system designers take advantage of the flexibility of a reconfigurable FPGA and the high-level programmability of a general-purpose DSP, Bittware officials say. A 64-bit, 66 MHz PCI interface and as much as 512 megabytes of SDRAM address applications requiring high bandwidth and data buffering, while SHARC link port interfaces, via the board's PMC+ interface, offer tight integration options for low-latency applications, company officials say.
"Because it supports both large frame buffering and low-latency stream I/O along with general purpose and special purpose compute elements, the Reef-PMC+ gives our customers almost unlimited versatility," says Jeffry Milrod, President of BittWare. "This board reinforces our commitment to providing flexible DSP solutions that address our customers' system design needs and help them get their applications to market more quickly."
It is for signal-processing applications such as image processing and radar that need to adapt various signals and frequencies in very noisy environments on the fly, Milrod says.
The host of features available on the Reef-PMC+ give designers the tools they need to implement complete DSP subsystems, including complex digital interfaces, general purpose compute engines, special purpose computing blocks, and large data buffers, Bittware officials say.
Milrod calls The Xilinx Virtex-II "great technology," and provides the Reef's "ability to completely reconfigure on the fly," he says. "The Virtex-II can be used for I/O, processing or both, with the DSP providing easily programmable high-performance processing."
The only drawback to million-gate FPGAs is programming each gate, Milrod says. "This can be a long and difficult process that includes a lot of debugging and testing." However, the tools for developing FPGAs are getting better and the advantages to the customer in terms of time-to-market, performance, and obsolescence mitigation are worth the effort, Milrod says.
The Reef's flexible digital I/O interface provides as many as 140 user I/O pins, each of which is individually configurable for any of the nineteen single-ended I/O standards and six differential I/O standards supported by the XC2V1000, including LVDS, SSTL, HSTL II, and GTL+, Bittware officials say. Any two I/O pins can be configured for use as a differential pair with terminations, providing maximum board flexibility, company officials say.
A BittWare SharcFIN application specific integrated circuit, or ASIC, provides a 64/66 PCI interface, flexibly interfaces the ADSP-21160 to peripherals such as Flash memory, and implements a flag and interrupt multiplexer, Bittware officials say. It also provides a SDRAM controller to interface the SDRAM to the DSP, the Virtex-II, and the PCI host, company officials say.
The Reef-PMC+ is compatible with any PMC capable carrier board. When attached to one of BittWare's PMC+ capable carrier boards, it supports BittWare's PMC+ extensions, which include four link ports and a serial TDM bus, Bittware officials say.
BittWare engineers also recently designed subsystems along the same lines as the Reef. The IS-6UHH-RF subsystems let system designers take advantage of the flexibility of a reconfigurable FPGA and the high-level programmability of nine general-purpose DSPs — all in one 6U CompactPCI slot, Bittware officials say.
Based on BittWare's Hammerhead board architecture, the IS-6UHH-RF subsystems give designers the tools they need to implement complex digital interfaces, general-purpose compute engines, special purpose computing blocks, and large data buffers, company officials say.
A 64-bit, 66 MHz PCI interface and as many as 2048 egabytes of SDRAM address applications requiring high bandwidth and data buffering, while SHARC link port interfaces offer tight integration options for low-latency applications. Sub-assemblies are available with one FPGA PMC card, a PMC site for additional I/O or with two FPGA PMC cards.
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