The true history of 2eSST

Motorola Computer Group recently pre-announced a VMEbus chip that will implement the 2eSST protocol, enabling dramatically higher bandwidth for VMEbus systems.

by Ben Sharfi

Motorola Computer Group recently pre-announced a VMEbus chip that will implement the 2eSST protocol, enabling dramatically higher bandwidth for VMEbus systems. That protocol, however, has been fully defined for some time and hardware supporting it has been on the market for nearly four years. The implementation of 2eSST in Motorola's coming Tempe chip, due to start sampling this summer, will rely on advanced high-power driver technology to achieve higher speeds, whereas the 2eSST-capable hardware already in the field relies on a simple but revolutionary backplane topology invented by Arizona Digital in Scottsdale, Ariz., known as VME320.

The nature of the Tempe approach is its ability to operate with legacy backplanes but requires new boards, while the VME320 requires new backplanes but accommodates legacy boards with small changes to their on-board protocols and FIFOs. The former is, thus, a good medium for conventional midlife upgrades to existing systems, whereas the latter, with far more performance headroom, is a bold new start. In any case, VME320 is technology agnostic: it can also take advantage of advances in bus driver silicon, and it has been applied to CompactPCI, PCI, and proprietary bus architectures in addition to VME. In both 2eSST approaches, OEMs may choose to support legacy transfer modes so that 2eSST-capable boards will be able to communicate with conventional boards at their more modest transfer rates.

The roots of 2eSST go back to the early 1990s, with the first of a string of midlife kickers for VME that would ultimately expand the 40 megabyte-per-second frontier of the 1980s to the 320 megabytes-per-second and faster realm today. Around the turn of the decade, a technique that was to become known as VME64 doubled the theoretical maximum VMEbus performance from 40 megabytes per second to 80 megabytes per second without challenging the technology of the day.

The brainchild of Performance Technologies of Rochester, N.Y., VME64 multiplexes 32 bits of data onto VME's previously unmultiplexed address bus, effectively turning it into a 64-bit bus. Subsequent VMEbus performance enhancements have all built on top of VME64.

Other, more technically challenging midlife kickers were explored, aired, and, in some cases, implemented in the mid to late 1990s. A suite of VMEbus extensions called VME64x, for example, included a two-edge (2e) transmission technique that effectively doubled theoretical data rates to 160 megabytes per second. The trick here was to read data on the falling and rising edges of a signal, essentially sending data at a 20 MHz rate on a 10 MHz VMEbus. Unfortunately, this required special ETL drivers that were available from only one supplier. Furthermore, by the time 2eVME was approved the VME320 had been announced at twice the performance using conventional drivers. Only one company, Force Computers of Fremont, Calif., implemented a product using VME64x.

Not included in the VME64x document was a source-synchronous (SS) overlay on the asychronous VMEbus, which had yet to be proven reliable using the bus drivers of the day. An SST protocol operates without the traditional transfer-by-transfer acknowledgement cycles of VME, clocking (strobing) data across the bus as fast as the sender and receiver can manage it. The promise here was to raise the 40 megabytes-per-second theoretical (25 megabytes per second actual) data rate to a 160 megabytes-per-second actual data rate and, in conjunction with 2e, double VMEbus bandwidth once again to 320 megabytes per second.

Getting to 320
In January of 1997, Drew Berding, president of Arizona Digital Inc. in Scottsdale Ariz., and consultant to Bustronic Corp. in Fremont Calif., announced his revolutionary star-backplane scheme to the VMEbus Standards Organization. In March, he followed that with a press conference revealing the technical details of VME320. At the time, Ray Alderman, executive director of the VMEbus International Trade Association in Scottsdale Ariz., dubbed VME320 "our silver bullet" against encroachments by CompactPCI."

The magic of VME320 (U.S. patent #5,696,667), said Alderman, is that "it's almost just a layout issue. "The rocket science is in how it's done using standard technology, but it's nothing exotic."

The real magic of VME320, as Berding sees things, is the use of simple synchronous protocols, which the clean, predictable electrical environment of VME320 enables. "You can't run synchronous protocols on normal backplanes because that requires incident wave switching," Berding explained. But in VME, a single pulse from a TTL driver is not sufficient to drive a signal through transition; in fact, the system relies on subsequent signal reflections on the backplane.

A VMEbus trace, in short, behaves like a slow, heavily loaded, low-impedance transmission line. Conventional ways of overcoming this might include terminating the lines to eliminate reflections, tweaking transceivers so as to tolerate reflections or boosting driver current. Tempe takes the third approach, which relies on a new derivative of the old ETL drivers defined by a VITA standards committee (VITA 2.1) in conjunction with Texas Instruments. Unfortunately, this brute-force approach to driving a conventional VMEbus backplane is a noisy, hot, single-sourced solution that only works for certain backplanes, with specified restrictions on which slots can accept boards.

The VME320 scheme, in contrast, addresses the problem by implementing a different topology than the traditional daisy-chained or "stitched" backplane topology, in which lines and their signals travel sequentially from Slot 1 to Slot 2 to Slot 3 and so on. With VME320, all lines are laid out in a star, radiating out from the middle or "common" slot (Slot 11 in 21-slot backplane) to all the other slots in what are essentially point-to-point connections. This in effect "makes the backplane look like a lumped capacitance [at Slot 11] rather than a transmission line," said Berding, "so when you drive it, you wind up with monotonic wave forms that don't ring back and forth." Rather than solving the reflection problems caused by transmission lines, the VME320 eliminates the problems by eliminating the transmission lines altogether.

"My waveforms are textbook," Berding said, "and VME320 does not use any technology that is not presently readily available." VME320 backplanes are readily available from stock from Bustronic Corp. at prices comparable to those of conventional VME backplanes. For those desiring to make their own backplanes, licenses are available for a very reasonable fee from Arizona Digital Inc.

The VME320 was first announced at 40 MHz (320 megabytes per second) but Berding claims that 1 gigabyte per second is not beyond reach and he has continued to optimize the scheme and achieve higher rates. Bustronic announced volume availability of 40 MHz GigaStar backplanes in early 1998 and, shortly thereafter, Arizona Digital and Bustronic demonstrated 66.625 MHz operation (above 500 megabytes per second), achieved by fine-tuning the 320 megabytes-per-second implementation.

At the time, Berding noted five items that could limit "the ultimate performance" of VME320: "the series inductance (L) from the furthest driver (including card stub and connector) to the common point; the total net capacitance (C), which includes the net traces, connectors, stubs and transceivers; the transient drive current of the drivers; driver skew and reflections on the electrically short traces."

In April 1999, Berding revealed the technology behind the tune-up and he had, again, addressed the issues in an unconventional way (U.S. Patent #5,930,119): by widening the longest traces to reduce L significantly (at the expense of a slight increase in total C) and by using a common region (slots 9, 10, 11, 12 and 13 in a 21-slot backplane) to further reduce L and eliminate the need for extra copper layers.

In early 2000 at the Bus & Boards conference, experts from Arizona Digital and General Micro Systems (GMS) of Rancho Cucamonga, Calif., demonstrated a 21-slot VME320 system with a pre-production version of the GMS OmniVME VME-to-PCI bus bridge chip. GMS has been incorporating the chip, which supports 2eSST transfer rates as fast as 533 megabytes per second, onto CPU boards since mid 2000 and it's also available to OEMs in source or binary format. In the demonstration, a frame buffer board sustained burst transfers to a video board over a fully loaded 21-slot VME320 backplane at in excess of 528 megabytes per second utilizing conventional drivers.

Most recently, Berding demonstrated an 80 MHz (640 megabytes per second) VME320 system, and Arizona Digital and GMS are collaborating on a cost-reduced version of the OmniVME chip. The new "miniOmni" will not have all the bells and whistles of the Omni chip, but it will be much more affordable. The intent of the miniOmni chip, which will be available to all interested parties, is to help drive VME320 to de facto standard status. It is being implemented in a CPLD. GMS also plans to provide a complete hardware reference design, so VME320 becomes, as Berding put it, "a no-brainer drop-in solution."

With 320 megabytes-per-second and higher transfer rates here now, 533 megabytes per second in reach and even higher rates on the near horizon, VMEbus becomes a far more capable platform for demanding high-end applications. The heavy traffic in leading-edge military and communications applications, for example, demand bandwidth, with their data-hungry Fibre Channel and ATM controllers, banks of Fast Ethernet controllers, simulation-grade graphics and huge amounts of multimedia data. As bandwidth demands grow even higher in the future, the "old" VMEbus will still be there to take care of the job.

Ben Sharfi is president and chief executive officer of General Micro Systems in Rancho Cucamonga Calif.

More in Computers