Motorola's 'VME Renaissance' is latest attempt to break through backplane databus bottlenecks

March 1, 2002
Members of an industry coalition led by Motorola Computer Group in Tempe, Ariz., are trying to break through a troublesome data bottleneck by increasing the capability and performance of the VME backplane databus eightfold.

LONG BEACH, Calif. — Members of an industry coalition led by Motorola Computer Group in Tempe, Ariz., are trying to break through a troublesome data bottleneck by increasing the capability and performance of the VME backplane databus eightfold.

Unlike previous attempts to supercharge the venerable VME 40-megabyte-per-second VME64 databus, this latest so-called "VME Renaissance" claims broad industry backing as well as backward compatibility with existing VME backplane chassis and printed circuit cards.

The Motorola-led initiative, which Motorola is calling the VME Renaissance, seeks to speed the VME backplane databus to 320 megagytes per second to start, and perhaps faster as the technology matures.

Industry experts say the VME Renaissance, which aims at defense, aerospace, medical, industrial automation, and other demanding embedded applications, is to give designers of embedded computers a fast bandwidth alternative in the near term as they await the promise of much faster serial switched-fabric interconnects expected before the end of this decade.

At least one nagging question remains: do VME systems designers have the technological and financial motivation to commit to a new VME backplane databus now with the promise of faster switched fabrics on the horizon?

VITA-standard 2eSSTThe program, announced earlier this year at the 2002 Bus and Board conference in Long Beach, Calif., will begin with Motorola's launch of a PCI-X to 2eSST VMEbus bridge chip called "Tempe," which implements the 2eSST protocol — an industry standard of the VMEbus International Trade Association (VITA) in Scottsdale, Ariz.

"Our complete commitment to moving the VMEbus technology forward is based on helping our current and future customers compete in their respective markets," says Jeffrey Harris, director of research and software architecture at Motorola Computer Group. The most promising military applications for VME Renaissance technology, he says, are radar, sonar, and signals intelligence.

The Tempe chip supports existing VMEbus protocols. It is designed to be backward compatible with existing VMEbus cards, which enables existing cards and new Tempe-enabled cards to work together in the same system. It also enables the cards to talk at regular VMEbus speeds and at improved 2eSST speeds — existing cards talk at regular VMEbus speeds, Harris says. The Tempe chip has a PCI-X bus host-side interface running as fast as 133 MHz, which provides transfer rates as fast as 1 gigabit per second. This is a 2X improvement over a 64-bit/66 MHz PCI interface, company officials say.

"There are a number of block transfer transactions in the VME specification, and 2eSST is the most efficient and powerful of them all," says Ray Alderman, executive director of VITA. "The '2e' part of the title stands for 'two edge.' This means that valid data is transferred on both the rising and falling edges of a synchronous clock provided by the sender of the data. The synchronous clock is the SST part of the definition (source-synchronized transfer)."

The VME Renaissance approach certainly is promising, but it was not the first to contribute a 2eSST product to the VME marketplace, claims Ben Sharfi, president of General Micro Systems in Rancho Cucamonga, Calif. Sharfi and his team designed a board called the OMNI about two years ago, which had VME running at a bandwidth of approximately 760 megabytes per second and was based on the star backplane invented by Drew Birding at Arizona Digital in Scottsdale, Ariz.

Sharfi says he welcomes Motorola to the 2eSST world. He admits that the OMNI, while having much higher performance than VME64, never really took hold in the VME market because most designers then were happy with the bandwidth of VME64 and did not believe they needed more speed, Sharfi says.

Tough sellSharfi cautions that the VME Renaissance approach might be a tough sell but says "I hope Motorola succeeds, because then I will be able to sell my product, too."

Berding developed a star-connected backplane around 1997 "demonstrating incident-wave switching, and we were off and running toward 2eSST," Alderman says. The new backplane was called "VME320" for the advanced speeds it could attain, he explains.

Then around 2000, General Micro engineers started working on their OMNI product. At around the same time, Bustronic engineers in Fremont, Calif., constructed VME320 star backplanes together with Berding. Also at about this time, Cetia — now Thales Computer in Raleigh, N.C. — also began working with the new 2eSST protocols and "developed silicon for the implementation of a new VMEbus interface chip with all the VME-64 and 2eSST mechanisms," Alderman adds.

The key difference between Motorola's solution and previous 2eSST implementations involves the new transceivers from Texas Instruments that Motorola uses, called SN74VMEH22501. These transceivers enable Tempe to achieve 2eSST speeds in existing VMEbus backplanes, not just in the star topology, Harris says. The TI parts are also backward compatible, he adds.

Market share is the key advantage Motorola officials have in pushing their product, Alderman says. With their partners, Motorola comprises about a quarter of the VME market, which will enable the company to drive the market, Alderman explains. If they succeed, then General Micro and Thales will benefit because they already have product that uses 2eSST, Alderman adds.

Market timingTiming is another reason for designers to look at the VME Renaissance; it is way too early to pick from the new generations of serial fabrics, Alderman says. There are 64 of them out there and it will be at least four to five years before there is any clear winner, he explains.

"Many users want to maintain their investments, particularly in VME, and the VME Renaissance offers them that capability," Alderman says.

"They can have complete backward compatibility, even with the new 2eSST performance enhancements, and they can also take advantage of the new fabric technologies at the same time," he says. "They can protect their investments in their present VME equipment and get the performance benefits of all the new technologies without 'forklift' upgrades. This makes a lot of sense to many VME users and manufacturers."

On many levels the VME Renaissance simply makes sense, says Jerry Braun, a commercial technology insertion project engineer at Naval Service Warfare Center (NSWC), Crane Division in Crane, Ind. "Any architecture enhancement that provides backward compatibility while increasing bandwidth and decreasing latency provides the military with tremendous flexibility when refreshing and inserting new technology into legacy equipment," he says.

The Motorola Tempe chip is expected to be available to all industry players through a third-party reseller sometime this fall.

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