FMC boards for FPGA-based embedded computing with Anemone technology on board introduced by BittWare

Aug. 23, 2011
CONCORD, N.H., 23 Aug. 2011. BittWare, a field-programmable gate array (FPGA) and digital signal processing (DSP) specialist in Concord, N.H., is introducing Anemone acceleration technology for FPGAs on VITA 57 FPGA Mezzanine Cards (FMCs) that attach to BittWare's existing Altera-based FPGA boards. Anemone offloads C language processing from FPGAs to help systems designers tackle the complexity of programmable hardware, finish projects quickly, reduce risk, and use less power, BittWare officials say. The Anemone104 chip is a many-core processor with 16 small RISC processors optimized for floating-point processing, all tied to the FPGA with innovative interconnects, says Jeff Milrod, BittWare president and chief executive officer.

CONCORD, N.H., 23 Aug. 2011. BittWare, a field-programmable gate array (FPGA) and digital signal processing (DSP) specialist in Concord, N.H., is introducing Anemone acceleration technology for FPGAs on VITA 57 FPGA Mezzanine Cards (FMCs) that attach to BittWare's existing Altera-based FPGA boards. Anemone offloads C language processing from FPGAs to help systems designers tackle the complexity of programmable hardware, finish projects quickly, reduce risk, and use less power, BittWare officials say.The Anemone104 chip is a many-core processor with 16 small RISC processors optimized for floating-point processing, all tied to the FPGA with innovative interconnects, says Jeff Milrod, BittWare president and chief executive officer.The first BittWare product using Anemone is the AA-FMC, which hosts four Anemone104 chips for total sustained performance as strong as 128 billion floating point operations per second. Anemone is an implementation of the Epiphany architecture from Adapteva, a startup company in which BittWare is an investor.

The Anemone104 runs on two Watts of total power, has on-chip distributed shared memory four megabits with 32 gigabytes per second of sustained memory bandwidth within each eCore. The Anemone104 has an internal inter-core mesh network, with separate data paths for on-chip and off-chip communications. Total on-chip, inter-core bandwidth is 128 gigabytes per second full duplex, with an additional eight gigabytes per second of off-chip bandwidth.

The FMC board has four Anemones arranged in a 2D mesh. All cores have direct memory mapped access to each other via the shared memory architecture and eMesh network. Link ports from two of the processors go to the FMC interface for direct connection to the host FPGA, which provides external memory interfacing and I/O connectivity. The complies with the VITA-57 (FMC) specification.

For more information contact BittWare online at www.bittware.com.

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-- Anemone FPGA-based co-processor introduced by BittWare to simplify digital signal processing for radar and SIGINT; and

-- C-programmable FPGA floating-point co-processor introduced by BittWare for radar, SIGINT, and SDR applications.

About the Author

John Keller | Editor

John Keller is editor-in-chief of Military & Aerospace Electronics magazine, which provides extensive coverage and analysis of enabling electronic and optoelectronic technologies in military, space, and commercial aviation applications. A member of the Military & Aerospace Electronics staff since the magazine's founding in 1989, Mr. Keller took over as chief editor in 1995.

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