DARPA seeks to speed defense electronics development by recycling blocks of IP tools

ARLINGTON, Va., 4 Nov. 2014. U.S. military researchers are trying to find ways to speed how long it takes to develop new defense electronics through the reuse and integration of blocks of intellectual property (IP).

Nov 4th, 2014
By Mil & Aero staff
By Mil & Aero staff
ARLINGTON, Va., 4 Nov. 2014. U.S. military researchers are trying to find ways to speed how long it takes to develop new defense electronics through the reuse and integration of blocks of intellectual property (IP).

Officials of the U.S. Defense Advanced Research Projects Agency (DARPA) released a request for information (DARPA-SN-15-04) last week for the Common Heterogeneous Integration and IP Reuse Strategies program.

This initiative seeks information from the defense industry on strategies for shortening electronics development time as well as vastly increasing performance and flexibility of RF electronic systems.

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DARPA researchers would like to achieve this through a combination of IP reuse and heterogeneous integration technology development. This combination is envisioned to dramatically enhance capabilities in the RF spectrum and lower costs.

The goal, DARPA researchers say, is to identify new approaches to accelerate technology adoption and to enable new design capabilities. Responses will help define possible future DARPA programs.

The program has three core challenges, DARPA officials say: creating an IP reuse ecosystem; developing integration technologies to combine process modules using standard interfaces; and integrating IP integration tools into a technology toolbox.

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The IP reuse ecosystem should help manage IP blocks from various process modules, such as silicon, gallium arsenide, gallium nitride, indium phosphide, and silicon germanium across a design and fabrication cycle.

Integration technologies should help electronics developers combine process modules interchangeably using standard interfaces. Together, these two technical areas form a technology toolbox that will enable a rapid and customizable design flow within current process technologies.

Managing the evolution of this toolbox will identify new process technologies for investment, and then quickly integrating them into a technology toolbox, DARPA researchers say.

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Explosive growth in mobile and telecommunication devices has pushed the semiconductor industry towards more integration of digital, analog, and mixed-signal blocks into system-on-chip (SoC) solutions, DARPA officials explain.

Advanced complementary metal oxide silicon (CMOS) has enabled this integration but also has led to a rise in design and processing costs. IP reuse is helping lower design costs, but this discipline largely is confined to digital technology.

To alleviate these challenges, DARPA researchers are trying to address reusable design in the digital and analog domains to enhance overall system flexibility and reduce design time.

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DARPA researchers are interested in ideas from companies and universities. Those interested should email responses no later than 1 Dec. 2014 to DARPA-SN-15-04@darpa.mil.

Email questions or concerns to DARPA's Daniel Green at DARPA-SN-15-04@darpa.mil. More information is online at https://www.fbo.gov/spg/ODA/DARPA/CMO/DARPA-SN-15-04/listing.html.

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