Military researchers eye built-in trusted computing and cyber security for complex digital chips

ARLINGTON, Va. – U.S. military researchers are asking for industry's help to make trusted computing and cyber security a routine part of digital integrated circuit design to protect advanced chips from known cyber attack strategies.

DARPA ERI:DA project focuses on integrated circuits for trusted computing and artificial intelligence
DARPA ERI:DA project focuses on integrated circuits for trusted computing and artificial intelligence
ARLINGTON, Va. – U.S. military researchers are asking for industry's help to make trusted computing and cyber security a routine part of digital integrated circuit design to protect advanced chips from known cyber attack strategies.

Officials of the U.S. Defense Advanced Research Projects Agency (DARPA) released a solicitation Wednesday (HR001119S0044) for the Automatic Implementation of Secure Silicon (AISS) program, which seeks make it easy to include defense mechanisms in systems-on-chip (SoC) design and fabrication.

The program aims balancing tradeoffs between advanced chip architectures and economic tradeoffs like power consumption, chip packaging size, and performance, while improving design productivity, DARPA officials say.

Throughout the past decade, cyber security threats have evolved from attacks only on software to threatening computer hardware like digital chips, as well as software. The popularity of internet-connected devices is encouraging hackers to shift their attention to chips that enable complex capabilities across commercial and military applications.

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No common tools or other solutions are in wide use today, DARPA researchers point out. Modern chips are complex and expensive just to design, let alone to include built-in security. Absence of automation makes incorporating security in chips a laborious and manual task that requires specific design expertise. The result: most of today’s chips are unprotected.

The objective of the DARPA AISS program is to enable a design tool and intellectual property (IP) ecosystem for digital chips where chip manufacturers could incorporate security naturally into chip design with minimal effort and expense.

The program also seeks to enable rapid evaluation of architectural alternatives that consider security as a crucial part of conventional design economics to bring power, speed, and security to advanced chip design.

AISS is a 48-month program divided into two technical areas: security and platform -- each with three phases spanning 15, 18 and 15 months. Developing technical teams to address each technical area is critical.

Related: DARPA eyes trusted computing, secure chip use, and semiconductor manufacturing

Security involves a subsystem that implements security features and interacts with related structures and services on- and off-chip. Platform involves a processor subsystem composed of processor, memory, and coprocessors or accelerators.

The AISS project calls for a cloud-based design environment with an open-source RISC-V platform as well as a commercial ARM processor for use in SoC design.

The AISS program is part of the DARPA Electronics Resurgence Initiative (ERI) to ensure far-reaching improvements in electronics performance and pushing the limits of traditional scaling. Essentially it seeks to simplify incorporating security into mainstream chip designs, as well as develop advanced defenses and countermeasures.

Related: DARPA chooses five to develop design tools for cyber security and trusted computing

Specifically, the program aims at protecting digital chips from side-channel attacks, reverse-engineering attacks, supply chain attacks, and malicious hardware attacks. It seeks to enable automatic generation of on-chip security subsystems that defend against supply chain, side channel, reverse engineering, and malicious hardware attacks, while interacting as necessary with off-chip support for key management, watermarking, obfuscation, authentication, provisioning, tracking, and analytics

The program also seeks to enable automatic generation of the processor subsystem or platform to customize processors, memories, logic accelerators, peripherals, and on-chip interconnects to optimize integration with the security subsystem.

By reducing the security burden of commercial silicon design, AISS aims at a sweeping effect on the commercial chip market by creating application-appropriate security that is baked in while significantly reducing development schedule.

Related: DARPA extends contract with Galois for trusted computing hardware design tools for cyber security

DARPA experts will brief industry on the AISS program from 9 a.m. to 6 p.m. on Wednesday 10 April 2019 at the DARPA Conference Center, 675 North Randolph St., in Arlington, Va. Register for the briefings no later than Monday 8 April 2019 online at www.cvent.com/d/s6qwvp. Those interested also can live-stream the briefings online at www.youtube.com/watch?v=h1JDXAnhsx8.

Companies interested in bidding to participate in the AISS program should submit full proposals no later than 20 May 2019 to the DARPA BAA Website at https://baa.darpa.mil.

DARPA officials say they plan to award several AISS contracts. The project should begin around October 2019, and should be worth about $75 million. Email questions or concerns to DARPA's Serge Leef at AISS@darpa.mil.

More information is online at https://www.fbo.gov/spg/ODA/DARPA/CMO/HR001119S0044/listing.html.

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