LONG BEACH, Calif., 18 Jan. 2006. A team of three embedded processing companies are proposing a new VXS processor mesh architecture about to move data at 112.5 gigabits per second within one chassis.
The companies -- Elma Bustronic of Fremont, Calif., TEK Microsystems Inc. of Chelmsford, Mass., and QinetiQ Real Time Embedded Systems (RTES) of Malvern, England -- made their announcement this week at the Bus and Board Conference in Long Beach, Calif.
Company officials say they will propose the VXS processor mesh architecture to the VME International Trade Association (VITA) in Scottsdale, Ariz., as a new standard to define alternative backplane topologies for VXS, otherwise known as VITA 41.
The VXS Processor Mesh throughput improves performance by six times over currently available technology, company officials say.
Elma Bustronic has also announced a 12-slot chassis to implement the VXS Processor Mesh, a hybrid backplane that implements two VME64x slots, three VME64x/VXS payload slots, and six VXS switch slots.
Each switch slot implements 20 x 4 links for a total throughput of 25 gigabits per second per switch slot. The system architecture supports as much as 7.5 gigabits per second of throughput between the I/O front end and the processing mesh and a total of 112.5 gigabits per second of aggregate throughput within the processing mesh itself.
"The VXS switch/processor mesh architecture clearly demonstrates both the longevity and expandability of the VME platform for high-performance embedded computing, says Andy Reddig, president and chief technology officer of TEK Microsystems.
"In one system, a user could simultaneously use four stages of interconnect evolution: VME64, RACE++, VXS payload and VXS switch cards," Reddig, continues.
"We consider the VXS Processor Mesh an instant architecture because it does not define any new backplane pin-assignments beyond those already defined within the VITA 41.0 base specification," says Michael Munroe of Elma Bustronic.
By comparison VITA 46.3 Serial RapidIO mesh slot supports four x4 links for a total of 5 gigabits per second per slot and an AdvancedTCA full-mesh slot supports 16 x4 links for a total of 18.75 gigabits per second per slot, company officials say.
Data-intensive applications such as synthetic aperture radar (SAR) can use the additional bandwidth of the VXS Processor Mesh architecture to scale to higher number of channels, higher bandwidth, or both, they suggest.
Together with dedicated off-board user I/O and two channels in each of the processor slots dedicated to the central dual-star switched fabric, the VXS Processor Mesh implements topologies such as traditional stars, dual stars, redundant dual stars, 4x pipelines (16x full duplex) 32x unidirectional rings or 16x bi-directional rings as well as a 4-channel (16x full duplex square mesh).
Because the central dual star VXS switched fabric common to all VITA 41 architectures serves each processor slot, this processor segment is is able to scale. Data can flow to and from any of the processor fabric slots.
The fat-pipe processor fabric segment enhances the other features of the VITA 41 architecture such as the I2C management bus, backwards compatibility to VME64x, PMC/XMC mezzanine sockets, rear transition slots, and the rugged VME64x mechanical architecture, company officials say.
For more information contact Elma Bustronic online at www.Bustronic.com, TEK Microsystems at www.tekmicro.com, or QinetiQ at www.qinetiq.com.
