HRL Laboratories eyes thermal management for 3DHI chip stacks in high-performance embedded computing

Questions and answers:

• What does the Minitherms3D project focus on? Developing scalable thermal-management technologies to control heat in future 3D heterogeneous integration (3DHI) chip stacks for high-performance electronics.
• What challenge does the Minitherms3D project address in 3DHI chip stacks? Thermal management in 3DHI chip stacks -- specifically reducing thermal resistance within the stack and externally, while managing hot spots and heat dissipation.
• What is the goal of the second phase of the Minitherms3D project? HRL Laboratories will demonstrate thermal management for a five-tier 3DHI chip stack by dissipating 6.8 kilowatts of heat, further improving heat management technologies for future microsystems.

ARLINGTON, Va. – Electronics thermal management experts at HRL Laboratories LLC in Malibu, California, are moving forward with a U.S. defense research program to develop new scalable thermal-management technologies to help control heat in future electronics architectures that involve 3D heterogeneous integration (3DHI) chip stacks.

Officials of the U.S. Defense Advanced Research Projects Agency (DARPA) announced a $7.8 million order to HRL Laboratories late last month for the second phase of the Miniature Integrated Thermal Management Systems for 3D Heterogeneous Integration (Minitherms3D) project.

Minitherms3D, sponsored by the DARPA Microsystems Technology Office, seeks thermal management technology scalable to an arbitrarily large number of high-power tiers in 3DHI chip stacks/v. This order brings the total value of the HRL Laboratories Minitherms3D contract to $14.7 million, up from the $6.9 million the company won in the project's first phase.

In the program's second phase, HRL Laboratories engineers will demonstrate thermal management of a stack of five equally powered tiers, with total dissipation of 6.8 kilowatts. In the project's first phase, HRL Laboratories mitigated hot spot mitigation for a stack of three equally powered tiers with total thermal dissipation of four kilowatts.

Five-tier chip stacks

Minitherms3D program goals include 3D stacking of five tiers with total heat dissipation more than 6.8 kilowatts with the heat rejection system limited to less than 0.006 cubic meters.

Continued rapid growth of compact high-performance microsystems is limited by inadequate integrated thermal management, including acquisition of heat from 3D integrated circuits, to the heat's transport and ultimate rejection to the ambient environment.

For example, the state of the art in 3DHI in high-performance embedded computing typically uses one tier of logic and several tiers of high-bandwidth memory. Stacking of logic is currently limited to low-power tiers.

Three-dimensional (3D) stacking of several tiers of high-power logic and other functional blocks, including radio frequency devices, offers significant advancement in future microsystems, but today is infeasible because of insufficient in-plane and out-of-plane heat acquisition from each tier, and poor thermal isolation between functional blocks.

Tell me more about 3DHI chip stacks ...

• A three-dimensional high-density interconnect (3DHI) chip stack places several layers of integrated circuits vertically to improve performance and reduce size, and enhances the overall functionality of electronic devices. This approach involves vertical integration, high-density interconnects, enhanced performance, thermal management, and increased complexity. Designers achieve this through wafer-level stacking, die-level stacking, and chip-on-wafer stacking. In computer servers and high-performance computing (HPC), 3DHI stacks can help improve the speed and power efficiency of chips, making it a good fit for artificial intelligence (AI) accelerators and advanced data and sensor processing.

Unoptimized heat transmission and rejection also result in large overall size of thermal-management hardware, which limits growth in system capabilities, particularly in radio frequency systems, image analysis, and high-performance computing applications such as artificial intelligence (AI) and machine learning.

The Minitherms3D project has two technical challenges: reducing thermal resistances within the 3D stack; and reducing thermal resistance external to the 3D stack.

Reducing thermal resistances within the 3D stack involves increasing in-tier heat transfer without increasing tier thickness. Regions of average heat flux more than 150 Watts per square centimeter along with localized hot spots more than 1 kilowatt per square centimeter in 3DHI tiers simultaneously must be managed thermally to maintain acceptable chip temperatures.

In a 3D stack, hot spot thermal management must rely on in-tier heat spreading, since interior tiers do not have direct access to top or bottom cooling. In a Si tier of 100-micron thickness, thermal conduction limits heat spreading to hot spot of 1-by-1 millimeter to 200 Watts per square centimeter with a temperature rise below 10 degrees Celsius over the rest of the tier.

Intense hot spots

Handling more intense hot spots requires increasing tier thickness or increasing thermal conductivity of tiers with processing compatible with very large scale integration (VLSI).

Reducing thermal resistances within the 3D stack also involves increasing thermal isolation between adjacent in-plane and out-of-plane functional blocks, as well as increasing heat removal from each tier while maintaining low thermal resistance.

Reducing thermal resistance external to the 3D stack, meanwhile, involves reducing link thermal resistance. Current approaches using thermal interface materials and cold plates have demonstrated 30 degrees Celsius per kilowatt of thermal resistance from the stack surface to the heat rejection component, posing a bottleneck in heat removal, and negating thermal resistance reduction inside the stack.

Volumetric heat rejection

This approach also involves increasing volumetric heat rejection capability while reducing heat rejection resistance to air. For given convection conditions and ambient temperatures, the volume of heat rejection to the ambient air -- or a heat sink -- increases linearly with heat rejection.

Minitherms3D is a four-year, three-phase program that began in early 2023. In addition to HRL Laboratories, Teledyne Scientific & Imaging LLC in Thousand Oaks, Calif.; and the Northrop Grumman Mission Systems segment in Linthicum Heights, Md., have been involved in the initial phases of the Minitherms3D program.

On this order, HRL Laboratories will do the work in Malibu, Calif.; West Lafayette, Ind.; Palo Alto, Calif.; and College Park, Md., and should be finished by August 2027. For more information contact HRL Laboratories online at www.hrl.com, or DARPA at www.darpa.mil/news/2023/chilling-stacked-chips.