SAN DIEGO, 8 April 2008. Engineers at Space Micro Inc. in San Diego has finished their fast codec integrated circuit (IC), which they developed under a contract from the U.S. Air Force Research Laboratory (AFRL) in Rome, N.Y.
Space Micro received application-specific integrated circuit (ASIC) devices in March from their silicon foundry and are under test and evaluation. This is a 2-year small business research (SBIR) phase II contract worth $750,000.
The research supports fast communications and particularly targets the U.S. Department of Defense's Transformational Communication Architecture Satellite (TSAT) program. The device is designed to be radiation hardened to more than 100 kilorads of total-dose radiation, and enables correction of errors in high-speed communication channels.
"This high-data-rate chip development uses advanced forward error correction algorithms and was previously demonstrated using an FPGA prior to implementation in a CMOS silicon ASIC," explains David Czajkowski, chief operating officer at Space Micro.
The data rate of this initial chip is 2.5 gigabits per second; the architecture supports a rate of 10 gigabits per second. The chip design uses Radiation Hardened By Design (RHBD) techniques. Forward error correction is achieved using a novel combination of Reed-Solomon and Turbo FEC coding techniques.
For more information contact Space Micro online at www.spacemicro.com.
