The King is dead; Long live FPGA Digital Down Converters (DDC)
It’s the end of an era. The industry standard GC4016 narrow band Digital Down Converters (DDC) device has finally been withdrawn by Texas Instruments. Well, almost.
The final last time buy expired earlier this month, and final deliveries have yet to be made. Some may take this to mean the DDC function has fallen out of favour, but it is just the way the DDC function is now implemented has changed because of the high-speed data throughput needed by today’s applications. Today the DDC is usually implemented as a part of something else in the same way as dedicated Universal Asynchronous Receiver Transmitters (UARTS), disk controllers and even Central Processing Units (CPUs) have been absorbed into multi-function devices.
Modern DDCs have gravitated into two platforms: the latest generation Analog to Digital converters (ADCs) and the application IP within FPGAs. Either solution positions the DDC exactly where it needs to be: the front end of the system where raw data needs to be unpicked to avoid overloading the CPUs or subsequent busses.
DDCs are perfect for applications such as Direction Finding (DF), SIGINT or Electronic Warfare (EW) where the system needs to be highly responsive, accurate and in the case of EW, low latency. This is because effective solutions need to know what the signals are, how to assess whether they are hostile, and where they are coming from with minimum fuss. Having the ability to extract data digitally at Radio Frequency (RF) speeds helps with this process and offers SWaP improvements by removing intermediate frequency (IF) stages completely to increase performance. In platforms such as UAVs, SWaP optimization is critical. Minimizing cards, even small form-factors such as VPX, is always beneficial as good RF DDCs implemented in FPGAs provide a very flexible way to save.
So what’s next?
For FPGAs, the high data rates cause challenges that even the latest generation of devices still struggle to overcome. For example, dealing with multi-GSPS within the FPGA itself requires parallelization, and data paths of 256 or 512 bits wide is not unusual. As FPGAs get larger, there will be room to expand the DDC by having more and more coherent channels, including mixing narrow and ultra-wide band modes.
Today, a generic DDC is an acceptable option, but there are still compromises on what can be implemented. Optimized DDCs are more effective as you get exactly what you need, but they do require expertise from design, to timing closure to verified fully synchronous behaviour. Unsurprisingly, the growing capabilities of local functions such as multi-core embedded ARM CPUs alongside FPGA gate fabric in SoC devices is adding to this by pushing the integration envelop to impressive levels.
