40 Gigabits/second Ethernet: It’s a Significant Step

April 3, 2017

The way Ethernet speeds have progressed is not totally obvious. It started at 10Mbps (Megabits per second) and moved up the scale as technology improved, going from 10Mbps to 100Mbps to 1Gbps to 10Gbps to 40Gbps…

Eh? Wait a minute. Why 40? Isn’t 100Gbps the next logical step? Well, in a perfect world it would be—but there are times when the commercial push for higher speed hits the pure physics of being able to reliably pass a signal down a channel. We are where we are because it was realized that 40Gbps was achievable within a short time frame - and 100Gbps was probably not.

Within the OpenVPX environment, 40Gbps is probably significant as it is probably the highest interconnect performance we can achieve with the current connector and copper backplanes. Optical backplanes will (likely) be required for anything faster. 

Of course, fitting this amount of switching capability into the 6U form factor is not easy, and all the normal challenges of hardware design apply. For example:

  • the signal integrity is crucial, so requires expert track routing at the board and backplane
  • the power required for the switch processing needs to be minimized, so a new fabric is used
  • the thermal output from the processing elements must be handled

To that latter point: Abaco has patented a new technology in this area which is transforming what’s possible. But I digress.

Need for speed

Why this need for speed? We’re beginning to see multi-core SBCs and DSPs which can handle data streams requiring  40Gbps speed. In particular, the High Performance Embedded Computing (HPEC) arena is one where the ability to process vast amounts of data from sensors of all sorts is required. 

The scale of the data required for applications like Synthetic Aperture Radar (SAR) is inexorably pushing up the number of bytes needing to be channelled through the HPEC system. These data streams are then processed in great detail in DSP cards, or multi-core SBC cards, or a combination of CPUs and GPUs. 

New and interesting ways are being devised by our customers to combine the various processing strengths of DSPs, GPUs, CPUs, and FPGAs to turn all the raw data into real, valuable information. The algorithms for Fourier transforms, pattern recognition, coordinate systems, filtering, and interpretation all have one thing in common—the need for bigger data streams.

In order to pass this data (both raw and processed) around the overall system, the network needs to run at very high data rates. At the heart of this network is an Ethernet switch, providing the exchange of data between the processing stages to eliminate potential bottlenecks in the overall system design.  

Ideally, it’s not just any old switch. Much preferable is a switch that’s fully managed with L3 capability to provide specific handling of traffic because of its priority or sensitivity. L3 switching means being able to make forwarding decisions on the IP (Internet Protocol) address rather than just the local Ethernet address. A fully managed L3-capable switch within the overall network architecture allows for the greatest flexibility when it comes to network design.

Alphabet soup

Some of the advances in data access methods used within some HPEC applications also have impact on the requirement for switches. One example here is how the Remote Direct Memory Access (RDMA) standards have required certain switch protocol features—and this leads us into an alphabet soup of WARP, RoCE, DBC, ETS, PFC and so on. These capabilities complement our RoCE capable 6U HPEC boards such as the IPN252, DSP282A and SBC627. RoCE enables very low latency, high throughput communication via a “kernel bypass” mechanism, enabling data to be moved over the network directly between application memory spaces, thus avoiding the overhead of the network stack.

Suffice it to say that it has proved essential for the HPEC product team and the switch product team at Abaco to work very closely together to characterize the problem and deliver the optimum solution.

That solution is the recently-released SWE540 6U OpenVPX switch. It represents the ideal combination of 40Gbps performance on the one hand with full management capabilities with L3 forwarding on the other—a combination not widely found in the industry. 

Providing such an embedded high-end 40Gbps capable switch means we’re giving our customers the networking solutions they need to achieve their data passing requirements within their HPEC applications. The SWE540 supports and complements our full range of SBCs, DSPs and software tools—all the building blocks needed to take radar and sensor data and turn it into the battlefield information which gives strategic advantage and keeps people safe.

With four times as much bandwidth as its predecessor, 40 Gigabits/second is indeed a significant step forward in delivering the performance that will be needed by the demanding embedded computing applications of tomorrow. 

About the Author

Richard Spiesman | Product Manager

Richard is a 40-year veteran of the embedded computing industry. Having graduated from UCLA with a bachelor of arts in economics, he joined Motorola before moving on to RAMIX, who were acquired by GE in 2003. He is now product manager for Abaco Systems’ networks and communications product line.

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