Overcoming the MIMO ADC channel synchronization challenge

Sept. 17, 2018

On the modern battlefield, dominating the electromagnetic spectrum is increasingly important. In order to do so, radar, SIGINT and electronic warfare systems must be able to cover wider and wider bands of the spectrum. For phased array systems, this means that more channels and higher sample rates are being deployed in order to maintain dominance of the spectrum.  As our adversaries rapidly ramp up their capabilities, the urgency to develop more sophisticated radar, SIGINT, and EW systems is only accelerating.

As channel count and sampling rates increase in these systems, there are some significant data processing and data movement challenges. Multi-element arrays like those found in radar and other RF apertures are increasingly driving the requirement for tight synchronization between many channels – sometimes in the thousands. In many such systems, a notable challenge faced by systems engineers is channel-to-channel synchronization. For these applications, precise channel synchronization within several degrees is essential. Channel-to-channel synchronization is often one of the first steps when developing a radar, SIGINT, or EW system - but it can take months to achieve.


To help jumpstart a radar, SIGINT, or EW development, Abaco’s SRS6000 delivers the ability to synchronize up to 32 1GSPS ADC channels with picosecond jitter out of the box. It is also scalable, with the potential to daisy-chain up to eight systems for a total of 256 synchronized channels – making it ideal for MIMO radar or EW systems. Migration to a deployed, rugged 3U VPX system is possible as well.

To overcome common synchronization challenges, the SRS6000 connects multiple FPGAs and ADCs through a JESD interface with a common clock generator, which can then be synchronized with a system clock generator. The system clock generator distributes: a master clock to all devices from which local device clocks are generated; synchronization pulses to each subsystem clock generator to align SYSREF (with JESD2014B, SYSREF is the master timing reference signal that aligns all the internal dividers from device clocks as well as the local multi-frame clocks in each transmitter and receiver) across all subsystems; and a synchronous trigger to initiate simultaneous data acquisition on all FPGAs.

Ensuring synchronization and deterministic latency through calibration is also critical. The SRS6000 additionally features an auto-calibration capability, meaning that it will automatically adjust its calibration routine in response to changes in cabling or setup.


Achieving channel-to-channel synchronization across a number of ADC converters connected to multiple FPGAs can be a challenge in any MIMO system – whether radar, SIGINT, or EW. JESD204B Subclass 1 provides a mechanism for achieving deterministic latency between the data converter and the FPGA - but there are a number of potential complications that the system designer must be aware of in order to synchronize multiple ADCs and FPGAs. The Abaco SRS6000 addresses these complications and provides users with up to 256 synchronized ADC channels sampling at 1 GHz.

The race toward electromagnetic dominance on the battlefield will not slow any time soon, so finding small ways to get the latest cutting edge technology into the hands of the warfighter is paramount – and Abaco is here to help.

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