These SDRAMs use an 8n-bit prefetch architecture to achieve high-speed operation. The 8n-bit prefetch architecture is combined with an interface that transfers two data words per clock cycle at the I/O pins. The DDR4 SDRAMs offer a data bus write Cyclic Redundancy Check (CRC), read preamble training, control gear-down mode, per-DRAM Addressability (PDA), output driver impedance control, and ODT.
