WASHINGTON - The National Aeronautics and Space Administration (NASA) has announced it is developing integrated circuits capable of withstanding extremely hot temperatures as part of landers for future missions to Venus.
The NASA Glenn Research Center Smart Sensing and Electronics Systems Branch is developing silicon carbide (SiC) for intelligent sensing and control electronic subsystems into harsh aerospace conditions - up to 1112 °F/600 °C - which is beyond the physical capabilities of silicon technologies. In particular, this procurement, NASA is seeking fabrication of particular integrated SiC device structures like junction field effect transistor (JFETs) and resistors via a particular fabrication process flow to specifications on NASA-provided 100 mm diameter 4H-SiC epilayered wafers using NASA-provided device-layout design files in Graphic Database System II (GDS) format. After the SiC device structures of the following statement of work are completed, the wafers will be delivered back to NASA for additional processing of bondpads and the back-side contact that will complete the formation of integrated circuits needed for NASA missions. The resulting IC chips produced will be used to implement prototype extreme-environment electronic systems and demonstrations.
Information regarding the layers, layout feature dimensions and layout rules for device pattern features to be present in the NASA design files is available online at https://www1.grc.nasa.gov/research-and-engineering/silicon-carbideelectronics-and-sensors/jfet-ic-tech-guide/.
The agency also ask that the contractor e-mail the data/documentation listed in each major step to the NASA’s technical monitor so that NASA can verify and quantify contractor progress and workmanship during the performance of this process. The contractor shall additionally also explicitly note any and all off-nominal observations and processing detected and provide accompanying relevant data. Examples of off-nominal observations include larger than 10% non-uniformities in deposited film thicknesses, or etch depths, de-lamination, buckling, or peeling of metal films, cracking or peeling of dielectric films, etc. in any wafer regions farther than 4 mm from a wafer edge.
More information, including diagrams and specifications, is available at https://sam.gov/opp/5aa1d634239747a58a985cd5d934d368/view. Questions can be directed to NASA's Lindsey McLellan at [email protected]. Responses are due 25 September 2023 at 5 p.m. EDT.
