Engineers at Chip Express in Santa Clara, Calif., needed a test and verification solution for design kits for their Laser Programmable Gate Array (LPGA) product families. TurboCheck a Register Transfer-Level (RTL) testability analyzer from SynTest Technologies, Inc. in Sunnyvale, Calif., met their needs.
"We recognize the importance of ASIC testability," says Ehud Yuhjtman, vice- president of engineering at Chip Express. "We chose TurboCheck so our customers could further shorten their design cycle by performing testability checks during an early design stage. With TurboCheck, our customers can avoid surprises at the tail end of their design cycle, and can meet their design`s testability requirements. This coupled with our fast-turn ASIC capability helps them achieve a time-to-market advantage."
TurboCheck-RTL identifies testability problems early in the design cycle. Removing these problems at the RTL stage improves test insertion, automatic test pattern generation, and fault coverage. Using Turbocheck-Gate - SynTest`s gate-level testability analyzer - or TurboCheck-RTL helps reduce the number of design iterations designers must make.
TurboCheck-RTL can identify most test rule violations, such as combination feedback loops, generated clocks, gated clocks, asynchronous set/reset, and floating busses. TurboCheck-Gate can pinpoint remaining test rule violations, including potential bus contention and accessibility to embedded RAMs and initialization of flip-flops and latches. - J.M.
For more information on Turbocheck and SynTest contact Benson Cheung by phone at 408-720-9956, by fax at 408-720-9960, by mail at SynTest Technologies, Inc., 505 S. Pastoria Ave, Suite 101, Sunnyvale, Calif., 94086, by e-mail at info@ SynTest.com, or on the World Wide Web at http://www.syntest.com.
Space Electronics engineers are using the M-Densus 3-D high-density memory module, pictured above, from Dense-Pac Microsystems for their RAD-PAK solid-state memory.
