Thirty-five picoseconds a week by John Rhea

WASHINGTON - Here is a mind-blowing statistic to stimulate your thinking: every week electronic circuits are getting faster by about 35 picoseconds and circuit densities are growing by 50,000 logic gates.

Dec 1st, 1998

Thirty-five picoseconds a week

by John Rhea

WASHINGTON - Here is a mind-blowing statistic to stimulate your thinking: every week electronic circuits are getting faster by about 35 picoseconds and circuit densities are growing by 50,000 logic gates.

That is the judgment of Phil Nigh, a scientist at IBM Microelectronics in Essex Junction, Vt. Nigh made his comments during an October panel session of the IEEE International Test Conference in Washington.

Nigh`s panel evaluated the 1997 roadmap of the Semiconductor Industry Association (SIA) and tried to determine if test equipment is up to the job of supporting the inexorable trend toward ever-greater speeds and densities.

The panelists pondered the question: would the semiconductor industry hit the wall because of an inability to test the expected devices? The testability question is still before the house, and the answers at this point are tentative.

This issue is a matter of more than passing interest to the system designers and integrators who have put their faith in a perpetual rate of progress that Intel founder Gordon Moore predicted. Moore said chip performance doubles every 18 months at no increase in price.

Nigh`s analysis is itself an extrapolation of Moore`s law, which Moore first annunciated in 1965. To take it a step farther, this law would represent a cumulative improvement in speed of about 2.7 nanoseconds over an 18-month product life cycle and an increase in functional density of nearly 4 million gates.

This range of improvement is within the SIA-established parameters. At a 1983 IEEE conference, for example, Robert Noyce, another Intel founder, projected device densities of 100 trillion gates by the year 2020. That number is particularly significant because it is also the number of synapses in the human brain.

This means the system houses have available to them the means to create new generations of weapon systems beyond the imagination of all but the most visionary today as long as the semiconductor industry manages to steer clear of any walls or pitfalls along the road to near-human intelligence. In this context, one can think of the military electronics industry as the apex of a pyramid of which state-of-the-art semiconductor research constitutes the base.

A disturbing note, however, is that everyone in the world will have access to the devices that will be the heart of future military systems, since all of these advances are likely to come from the highly competitive commercial world. The same devices will be available to the likes of Saddam Hussein in an increasingly borderless world that the Internet and falling barriers to global trade make possible.

Real or imagined roadblocks are not new. It was only 10 years ago, for example, when experts said semiconductor lithography was at the limits of its capabilities, points out Wayne Needham, a scientist at Intel Corp. in Chandler, Ariz. A decade ago, scientists said optical methods could not achieve geometries below 1 micron and believed that processes were not capable of more than two layers of metal.

"CMOS was forecasted to die a slow painful death and be replaced by silicon-on-sapphire or gallium arsenide technology," Needham told the IEEE International Test Conference audience.

So what happened? Academic and industrial researchers faced up to the challenges of the roadmaps of the time and responded with such measures as deep ultraviolet lithography, new packages, voltage scaling, new design tools, and fast test equipment, Needham says.

Today, the SIA roadmap predicts that the test industry will face the challenges of I/O bus speeds of 3 GHz, chip pincounts of more than 7,000, and unprecedented integration of digital, analog, and memory core elements by 2012.

The response, Nigh says, should be a change in the testing philosophy from the functional tests of the past to what is becoming known as structural testing.

Functional testing is just that: it tests all functions of a device as they would be performed in actual usage. "By this definition, automatic test equipment [ATE] resources, such as speed and pincount, must always equal or surpass product requirements," Nigh notes.

The semiconductor industry no longer can afford to spend the money or the time that such thorough testing requires, Nigh says. The SIA roadmap projects that a single-site performance tester in 2012 will cost $26 million to $53 million, and that product time-to-market pressures are increasing the importance of fast debug and diagnostic turnaround times.

Instead, Nigh advocates structural testing in which the producer implements some form of design-for-test - also known as DFT - that enables users to create tests automatically. "As the industry moves from functional toward structural test, the goal of test will change from `ensuring the IC performs its function` to `ensuring the IC has no manufacturing defects`," he says. "Design functional verification will be totally independent from manufacturing test."

This does not mean the elimination of ATE, Nigh says, but rather a change in its role. Circuit designers will always need some functional testing, he says, although not all of the pins will have to be run at full speed. Moreover, what designers have traditionally thought of as digital testers will have to be flexible enough to test embedded analog macros on applications-specific integrated circuits.

"There is no `wall`," adds Burnell West, a researcher at the Schlumberger Technologies ATE Division in San Jose, Calif. "What there is consists of hills to climb, and with the climbing of these hills we will be able to see the structure and nature of the hills beyond them."

The contribution of the IEEE panel was to introduce a note of urgency to the whole issue. "It is critical to understand the fundamental barriers we are facing, not necessarily the exact date that we hit these barriers," Nigh says. "By identifying these `walls,` we can define a research and development game plan to ensure that test does not limit the ability to exploit the advanced technologies being developed."

For further encouragement, it might be helpful to refer to another law promulgated at Intel: "All chips eventually cost three dollars - if they don`t cost less."

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