Packaging COTS chips for environmentally demanding applications

Military agencies, defense companies, and even major universities are joining in the effort to find innovative integrated circuit and board packaging approaches to enable systems designers to use commercially developed components in military and aerospace platforms

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By J.R. Wilson

Military agencies, defense companies, and even major universities are joining in the effort to find innovative integrated circuit and board packaging approaches to enable systems designers to use commercially developed components in military and aerospace platforms

Years ago defense applications dominated technology development and military specifications were the norm. In those days, acquiring microchips packaged to meet the rigors of military applications — especially in aerospace — was largely a question of cost. Today, however, telecommunications drives technology development, and military systems designers can rarely afford mil-spec components — or find anyone willing to do them for military and aerospace systems designers who make up less than one percent of the electronic component market.

As a result, military program managers must find ways to use chips with commercial off-the-shelf (COTS) packaging that are not designed specifically to withstand harsh environmental conditions so often present in military applications.

A new approach to that dilemma is the core component of a joint effort by the U.S. Army Aviation and Missile Command (AMCOM) in Huntsville, Ala., and Lockheed Martin Missiles and Fire Control in Grand Prairie, Texas. This effort comes under the auspices of the U.S. Army Manufacturing Technology (ManTech) program. Army officials say they hope to develop a technology them that will make commercial chips viable in the rugged environments of military use. Furthermore, Army officials want to convince industry that this new technology not only is cost-effective, but also adds value.

Rather than attempt to solve all environmental problems at once, researchers involved with the ManTech effort are concentrating on moisture-related reliability issues first. The aim is to create near-hermetic protection for microchips used in military applications. However, they believe their approach also can address such problems as temperature range, vibration, shock, and perhaps even radiation.

Manufacturers have been steadily eliminating high-cost, low-demand ceramic packaging choices, long considered the gold standard for reliable packaging. Instead, commercial plastic encapsulated microcircuits (PEMs) now come off highly automated production lines intended for typical office applications.

In a harsh military environment, however, such PEMs are prone to intermittent and catastrophic failures. Nor are they designed to withstand two decades of storage, then operate reliably, as often is the case with missile applications. Reliability analysts trace many of the resultant failures to water-based corrosion on the IC die or interconnect bond pad.

Water-based corrosion

"There are two problems with the commercial process of using a gold wire on an aluminum alloy," says Chuck Reusnow, Lockheed Martin program manager. "It can cause what's called 'purple plague', which can cause an unreliable electrical interconnect. The bigger problem is the aluminum can react with moisture to form aluminum oxide, which is an insulating material that can swell up and actually lift the wire off the bond pad."

Such problems are not acceptable, says Peter Black, program manager for WASPP — ManTech's Wafer Applied Seal for PEM Protection project. "These kinds of defects cannot be tolerated while the systems are in use," Black explains. "Military parts, with hermetic seals, don't have those problems, but those parts are going away and we have to find a way to use these COTS parts."

The WASPP solution has been the application of the Dow Corning's ChipSeal coating method from Dow Corning in Midland, Mich. This approach layers hydrogen silsesquioxane (trade name: Flowable Oxide or FOx) and silicon carbide over the passivation on the surface of a semiconductor wafer. A planarizing material, FOx relieves stresses across the chip surface while silicon carbide, a hydrophobic material, prevents cracks and pinholes.

In addition, chip designers pattern two layers of metal over the aluminum bond pads to protect the interconnects on each IC. The top layer is 500-nanometer-thick gold because of the metal's resistance to corrosion and compatibility with the gold wire bonds. A 350-nanometer-thick layer of titanium tungsten forms a barrier metal between the aluminum bond pad and the top layer of gold to prevent gold-aluminum diffusion and delamination.

Black says his team looked at several organic and inorganic coatings, including fluorocarbon polymers, polyimides, doped silicate glasses, and silicon carbides. However, team members did not want to develop any materials and so selected the Dow Corning process as the most mature available. While that process has been optimized for technical performance and cost, the project continues to seek ways to improve processing for the chip seal.

New coating approaches

"We're trying to use this relatively new coating technology and provide enough benefits for everyone in the electronics industry — all the way from the semiconductor manufacturers to the packaging people to the users," Black says. "The semiconductor community gets a lower-cost or no-cost-added process with increased reliability. The packagers get higher yields because the devices are more robust and they may be able to use cheaper materials to coat the devices because they already have more resistance to humidity and corrosion. The end users also are looking for higher reliability, especially the military and industrial users.


Chip designers are devising a variety of ways to mitigate wire bond corrosion with protective layers of metal.
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Attempts to improve chip packaging also can offer some side benefits. "In some cases, this coating also has been shown to improve performance, especially in gallium arsenide semiconductors, which usually are used for high frequency applications in the military," Black says. "Initial tests with these coatings have shown a 15-to-25 percent increase in performance because the material has a lower dialectic constant than silicon nitride."

Previous efforts in the defense industry to apply external IC protection — such as desiccants, conformal coatings, specialized hermetic die packaging, and "cocooning" (a hermetic enclosure around the entire circuit card assembly) — have largely failed. Desicants and conformal coating failed because of technical problems, while hermetic die packaging and cocooning failed because of cost, availability, or weight/volume issues, experts say.

Another approach — removing the die from commercial plastic packages and repackaging them into hermetic modules — may be possible in dealing with small volumes to replace obsolete components in old weapons systems. However, Black says, experts do not yet know if that process may be subject to latent failures in fielded systems down the road.

Without viable reliability improvement solutions in place, expensive qualification tests have been necessary to see if commercial PEMS can stand up to harsh military applications. Even then, such PEMs are subject to unannounced material and process changes by the manufactures that can invalidate those tests and lead to unexpected failures in the field.

In light of that, military experts were heartened by a recent U.S. Air Force program demonstrating ChipSeal's effectiveness with a survival rate approximating mil-spec hermetic parts during a 1,000-hour highly-accelerated stress test (HAST).

In addition to Lockheed Martin and Dow Corning, the WASPP team includes members from across the industry spectrum who have invested their own money in the effort. Fairchild Semiconductor in South Portland, Me., is providing the silicon-based manufacturing, TriQuint Semiconductor of Richardson, Texas, is providing the gallium arsenide. Chip Supply in Orlando, Fla., is the packaging and wafer provider while AMKOR in Wichita, Kan., serves as an independent test organization. In addition, Rockwell Collins in Cedar Rapids, Iowa supplies commercial aerospace and military customers and recently signed on as a subsystem integrator.

Packaging applications

"We had our own devices fabricated with the ChipSeal coating — a set of RS422 line drivers and receivers from National Semiconductor [of Santa Clara, Calif.]," Black says. "We selected those because they are being used in an upgrade to the ATACMS (Army Tactical Cruise Missile System) guidance computer. Lockheed Martin is the systems integrator for that and our parts will be tested along with standard off-the-shelf parts for that program.

"We also will be doing several tests of our own, which we are very close to beginning." Black adds. "AMKOR will do independent testing and each of the team members will do their own in-house testing. Those will all be full military qualification tests."

Most of those tests will concentrate primarily on resistance to moisture-induced corrosion and thermal cycling. However, some of the ATACMS qualification tests also will look at radiation and vibration.


Aluminum in chip packages can be a problem with it creates aluminum oxide, which can lift bonding from the package. Several approaches seek to protect the aluminum with other metal layers.
Click here to enlarge image

"We're actually beefing up the radiation testing because the space people are interested in seeing if the new coating has any impact on radiation tolerance," Black explains. "We doubt it will improve that tolerance, but the first coating is annealed at 400 degrees Celsius and there was some concern that might reduce some of the rad tolerance of some devices. In addition to total dose, we also are now looking at neutron high dose rates, proton, and heavy ion tests."

AMCOM officials also recently awarded two small business innovative research (SBIR) contracts that will apply lessons learned from WASPP to new material combinations that can be developed to serve as electronic encapsulants. Utility Development Corp. in Livingston, N.J., and TRITON Systems of Chelmsford, Mass., received those awards in late February. According to the SBIR solicitation, "the primary purpose of the encapsulant will now be to provide mechanical, thermal, and material compatibility between the mounting substrate (printed circuit board) and the IC contained within the encapsulation."

The SBIR work will be in three phases. The first phase will investigate the electronic packaging characteristics of existing polymers, while the second phase will look into the most economic and efficient methods for applying selected materials. The third phase will examine the dual use in commercial applications of packaging materials that improve the reliability and performance, while lowering the cost, of nearly all electronic components used in weapons systems.

"The beauty of the ChipSeal coating is that you can use some of the more advanced, very thin packaging," Black says. "It enables the military to use these advanced packages without concern for the reliability problems caused by moisture and ionic contamination. If you have devices with the ChipSeal coating, you don't have to worry about moisture getting into the package. Then you can look at doing what I call moisture management, keeping it off the surface of the die."

Reusnow says the ChipSeal process also alleviates many restrictions on the use of other materials to address other environmental issues.

The role of DARPA

Another packaging research program is at the Defense Advanced Research Projects Agency (DARPA) in Arlington, Va., This program is called Heat Removal by Thermo-Integrated Circuits — HERETIC, for short.

According to DARPA's program overview: "The focus of this program is at chip and board levels. The program aims to exploit recent developments in micro-fabrication technologies (such as micro-machining) and advances in heterogeneous materials integration in microelectronics to develop novel heat removal devices that are integrable with electronics and optoelectronics. There are four areas of interest: (1) core technology development, (2) integration and packaging, (3) modeling and simulation and (4) demonstrations."

The problem with thermal management in most commercial electronic and optoelectronic systems, as outlined by DARPA, is similar to what Army researchers found with respect to moisture: The standard approach is cost-effective and efficient for non-critical applications in relatively benign environments. Yet in the often thermally harsh environments of military applications new or novel approaches are necessary to develop solid-state and fluidic heat removal devices.

"Of particular interest are heterostructure integrated thermionic (HIT) or thermoelectric devices and phase-change heat removal devices," according to DARPA. "Other devices of interest include micro-machined synthetic jets or nozzles and channels that can act as micro-circulators of air or fluid in individual chip-packages; these micro-coolers, however, must be integrated with chip packages. Micro-machined devices may also include thermionic emitters that exhibit credible cooling when integrated with active electronic or optoelectronic devices that generate waste heat."

Several corporations and universities have undertaken research as part of HERETIC, including CFD Research Corporation in Huntsville, Ala., the Rockwell Science Center in Thousand Oaks, Calif., Carnegie Mellon University in Pittsburgh, Florida International University in Miami, Georgia Institute of Technology in Atlanta, the Jet Propulsion Laboratory/California Institute of Technology in Pasadena, Calif., Stanford University in Palo Alto, Calif., the University of California at Los Angeles, the University of California at Berkeley, the University of California at Santa Barbara, the Massachusetts Institute of Technology in Cambridge, Mass., the University of Maryland in College Park, Md., the University of North Carolina-Charlotte, and the University of Utah in Salt Lake City.

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