Tucson, Ariz., 17 July 2008. Engineers at Xilinx in San Jose, Calif., demonstrated how their FPGAs (field programmable gate arrays) can aid in radiation-hardened system design.
In their booth at the conference Xilinx demonstrated a Fault-Injection Upset Simulator, which is based on fault injection and uses the same hardware as in-beam testing. The system, developed by the Radiation Test Consortium (XRTC), leverages the reconfigurability of Xilinx FPGAs and is capable of injecting simulated upsets at a rate of more than 3 million per minute while verifying design functionality.
Xilinx engineers Carl Carmichael, Tony Duong, Austin Lesea, Greg Miller, Gary Swift, Chen Wei Tseng, and Yiding Wu also shared authorship of a Poster Paper on "Upset-Induced failure signatures, recovery methods, and mitigation techniques in a high-speed serial data link for space applications." The other authors were Keith Morgan, Michael Caffrey, Mark Dunham, Paul Graham, and Heather Quinn of the Los Alamos National Laboratory as well as Roberto Monreal of SEAKR and Greg Allen of the NASA Jet Propulsion Laboratory.
Quinn and Graham of Los Alamos National Laboratory also presented a paper on Xilinx technology at the conference. It was titled "An automated approach to estimating hardness assurance issues in triple-modular redundancy circuits in Xilinx FPGAs.
