SAN JOSE, Calif., 8 July 2009. he Japan Aerospace Exploration Agency (JAXA) has adopted the Cadence Virtuoso IC 6.1 custom design platform and the Cadence Virtuoso Spectre Circuit Simulator from Cadence Design Systems Inc. Building circuits to be used in space exploration under extreme conditions without malfunctions requires the accurate modeling of multiple factors of disturbance, and then the use of those models to test the chip designs. JAXA engineers selected Cadence Virtuoso technology to help develop this critical circuitry.
JAXA engineers had been examining EDA products for its research-and-development department's designs, which include circuits that will be exposed to radiation in space that generates random noise and can result in circuitry malfunctions, says a company representative. To address these effects, engineers must consider parasitic elements of their designs; yet, prior to using Virtuoso IC 6.1 technology, JAXA had not found satisfactory results from their examination.
"It is critically important for JAXA to develop test LSIs to ensure that the devices will work in space," says Satoshi Kuboyama, manager of Electronic Devices and Materials from Aerospace Research and Development Directorate, JAXA. "By using Virtuoso IC 6.1, we are able to predict behavior of circuits and verify many corner cases at one time, and development and experimentation time will be significantly reduced. This represents one big step forward in enabling space exploration."
JAXA engineers also adopted the company's Virtuoso Layout Suite XL.
