Managing Signal Integrity Challenges for Success in High Performance Embedded Computing Systems

April 17, 2024
Discover the critical shift in VPX systems' signal integrity at Gen4+ speeds and 100-Gigabit Ethernet, explored through the lens of VITA 68.3 standards development, real-world design cases, and high-performance cooling techniques in this insightful webcast.

April 17, 2024

2:00 PM ET / 1:00 PM CT / 11:00 AM PT / 7:00 PM GMT

Duration: 1 hour

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Data rates are at the very limit of what VPX can support, and they are impossible to achieve without careful analysis, simulation, design practices, and verification approaches.   

This issue prompted VITA to start the VITA 68.3 Signal Integrity for Gen4+ Speeds working group to analyze the problem and draft standardized approaches to address these problems.  

This webinar looks at the current state of VITA 68.3, as well as some real-world design use cases involving high-speed switches from Interface Concept and backplanes from Elma, and the lessons learned by both teams. They will also discuss HPEC performance with reference to the cooling techniques considered that include 48.2 Conduction and 48.8 AFT, that allow the switches to operate at full performance under wide temperature and full bandwidth use cases. 


Mark Littlefield, Director, System Products, Elma Electronic

Mark Littlefield is director of systems products for Elma Electronic.  He is an active contributor to multiple VITA and SOSA technical working groups, including the SOSA small form factor (SFF) sub-committee, and was co-chair of the VITA 65 OpenVPX working group. He has more than 25 years of experience in embedded computing, where he has held a range of technical and professional roles supporting defense, medical, and commercial applications. Mark holds bachelor's and master’s degrees in control systems engineering from the University of West Florida. 

Franck Lefevre, Director, Technical Sales, Interface Concept

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