Software design tools for the rapid deployment and verification of FPGAs using VHDL introduced by Aldec

Feb. 9, 2021
Active-HDL enables FPGA designers to take advantage of features in the latest revision of VHDL and helps improve design verification efficiency.

HENDERSON, Nev. – Aldec Inc. in Henderson, Nev., is introducing enhanced Active-HDL to support for new features in the VHDL-2019 (IEEE 1076-2019) design language software.

These features simplify the language, lift restrictions of earlier versions, and introduce new application programming interfaces (APIs). The release also adds support for release 2020.08 of the open source VHDL verification methodology (OSVVM).

Active-HDL is an integrated design environment that includes hardware design language (HDL), graphical design tools, and RTL/gate-level simulator for the rapid deployment and verification of field-programmable gate arrays (FPGAs).

These features, combined with the latest revisions to VHDL, empower engineers to create, maintain, re-use and easily verify their designs.

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Support for OSVVM 2020.08 gives users access to the free and open-source methodology's new requirements tracking, updated scripting, AXI4 verification components, and model independent transactions.

The latest version of Active-HDL also sees SystemVerilog enhancements like support for multidimensional arrays, preliminary support of unresolved user-defined nettypes, and preliminary support for unique constraints.

It also has several non-standard extensions to SystemVerilog in the latest release of Active-HDL. These include driving variable type outputs of clocking blocks with a continuous assignment, use of foreach loops iterating over the elements of a subarray, and assigning a virtual interface with a modport to a virtual interface without a modport.

For more information contact Aldec online at

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