WRIGHT-PATTERSON AFB, Ohio – U.S. military researchers needed a company to develop a large-scale efficient correlator able to operate at high dynamic range for new generations of passive sensing, real-time synthetic aperture radar imaging, and jam-resistant communications. They found their solution from Epirus Inc. in Torrance, Calif.
Officials of the U.S. Air Force Research Laboratory at Wright-Patterson Air Force Base, Ohio, announced a $5.4 million contract to Epirus on Tuesday for the Massive Cross-Correlation (MAX) project.
The MAX program seeks to capitalize on the advantages of signal processing that uses analog processing, hyperdimensional computing, or hybrid approaches.
MAX seeks to achieve at least a 100 times improvement in power efficiency and information processing density compared to state-of-the-art digital signal processing systems. The Air Force research lab awarded the contract to Epirus on behalf of the U.S. Defense Advanced Research Projects Agency (DARPA) in Arlington, Va.
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The mathematical function of correlation lies at the heart of virtually all digital signal processing systems, using several computationally expensive digital fast Fourier transforms to move between the time and frequency domains to compare signals for similarity, researchers explain.
In addition, real-world impairments and background noise in the environment requires a correlator to use power-hungry digital signal processing to produce additional processing gain for high dynamic range operation, which is necessary to sense weak signals below the noise floor.
The resulting correlation computation, researchers say, scales exponentially in power. Therefore, today’s systems require racks of graphics processing units (GPUs) and field-programmable gate arrays (FPGAs) to perform correlation over a relatively small frequency range with low bandwidth. This power scaling relationship is what prevents operation at high frequencies, large bandwidths, and high dynamic range simultaneously.
The Massive Cross Correlation (MAX) program seeks to achieve a disruptive leap forward for correlation in advanced CMOS nodes to fulfill the long unrealized potential of analog computation in future U.S. military sensing, imaging, and communications systems.
Epirus researchers will attempt to achieve 100 tera-operations per Watt power efficiency at 72 decibels hardware dynamic range, 120 decibels of total system dynamic range, sample rate of 5 gigasamples per second; and power consumption of 10 Watts -- all in a size of 1.7 by 1.7 by 0.25 inches.
The company has a goal of demonstrating an analog correlator implemented in 22-nanometer CMOS, with 100x performance/power improvements compared to a state-of-the-art digital FPGA implemented in 14-nanometer CMOS.
The four-year MAX program will have an 18-month first phase to demonstrate efficient scalable analog circuits with a correlation efficiency of at least 500 tera-operations per Watt at 48 decibels of hardware dynamic range; a 15-month second phase to demonstrate a small-scale analog correlator with better than 100 tera-operations per Watt at 72 decibels; and a 15-month third phase to demonstrate a large-scale analog correlator with 100 tera-operations per Watt efficiency, 72 decibels hardware dynamic range, and 48 decibels signal processing gain in a 10-Watt form factor with 5 gigasamples per second throughput.
For more information contact Epirus online at www.epirusinc.com, DARPA at www.darpa.mil, or the Air Force Research Laboratory at www.afrl.af.mil.
