ARLINGTON, Va. – Two U.S. technology companies are moving forward on a military scalable thermal management technologies initiative to help control heat in future electronics architectures that involve 3D heterogeneous integration (3DHI) chip stacks.
Officials of the U.S. Defense Advanced Research Projects Agency (DARPA) in Arlington, Va., are asking HRL Laboratories LLC in Malibu, Calif.; and Teledyne Scientific & Imaging LLC in Thousand Oaks, Calif., to move to the second phase of the Miniature Integrated Thermal Management Systems for 3D Heterogeneous Integration (Minitherms3D) project.
The project's second phase will demonstrate thermal management of a stack of five equally powered tiers, with total dissipation of 6.8 kilowatts. Both companies completed the project's first phase that focused on hot spot mitigation for a stack of three equally powered tiers with total thermal dissipation of four kilowatts.
The third phase of the 3D chip stacks cooling project -- if it continues -- would demonstrate system level thermal resistance and volumetric heat rejection targets in a simulated application.
3DHI chip cooling
Teledyne Scientific & Imaging won a $9.8 million order for Minitherms3D phase two in late January, while HRL Laboratories won a $7.8 million order for Minitherms3D phase two last August. Minitherms3D seeks thermal management technology scalable to an arbitrarily large number of high-power tiers in a 3DHI chip stack.
Continued rapid growth of compact high-performance microsystems is limited by inadequate integrated thermal management, including acquisition of heat from 3D integrated circuits, to the heat's transport and ultimate rejection to the ambient environment.
For example, the state of the art in 3DHI in high-performance computing typically uses one tier of logic and several tiers of high-bandwidth memory. Stacking of logic is currently limited to low-power tiers.
Three-dimensional (3D) stacking of several tiers of high-power logic and other functional blocks, including radio frequency devices, offers significant advancement in future microsystems, but today is infeasible because of insufficient in-plane and out-of-plane heat acquisition from each tier, and poor thermal isolation between functional blocks.
Heat transmission and rejection
Unoptimized heat transmission and rejection also result in large overall size of thermal-management hardware, which limits growth in system capabilities, particularly in radio frequency systems, image analysis, and high-performance computing applications such as artificial intelligence (AI) and machine learning.
The Minitherms3D project has two technical challenges: reducing thermal resistances within the 3D stack; and reducing thermal resistance external to the 3D stack.
Reducing thermal resistances within the 3D stack involves increasing in-tier heat transfer without increasing tier thickness. Regions of average heat flux more than 150 Watts per square centimeter along with localized hot spots more than 1 kilowatt per square centimeter in 3DHI tiers simultaneously must be managed thermally to maintain acceptable chip temperatures.
In a 3D stack, hot spot thermal management must rely on in-tier heat spreading, since interior tiers do not have direct access to top or bottom cooling. In a Si tier of 100-micron thickness, thermal conduction limits heat spreading to hot spot of 1-by-1 millimeter to 200 Watts per square centimeter with a temperature rise below 10 degrees Celsius over the rest of the tier.
Intense hot spots
Handling more intense hot spots requires increasing tier thickness or increasing thermal conductivity of tiers with processing compatible with very large scale integration (VLSI).
Reducing thermal resistances within the 3D stack also involves increasing thermal isolation between adjacent in-plane and out-of-plane functional blocks, as well as increasing heat removal from each tier while maintaining low thermal resistance.
Reducing thermal resistance external to the 3D stack, meanwhile, involves reducing link thermal resistance. Current approaches using thermal interface materials and cold plates have demonstrated 30 degrees Celsius per kilowatt of thermal resistance from the stack surface to the heat rejection component, posing a bottleneck in heat removal, and negating thermal resistance reduction inside the stack.
This approach also involves increasing volumetric heat rejection capability while reducing heat rejection resistance to air. For given convection conditions and ambient temperatures, the volume of heat rejection to the ambient air -- or a heat sink -- increases linearly with heat rejection.
Four-year program
Minitherms3D is a four-year, three-phase program with 18-month phase 1, 18-month phase 2 option, and 12-month phase 3 option. Phase 1 focuses on hot spot mitigation for a stack of three equally powered tiers with total thermal dissipation of four kilowatts. Phase 2 will demonstrate thermal management of a stack of five equally powered tiers, with total heat dissipation of 6.8 kilowatts. Phase 3 will demonstrate system level thermal resistance and volumetric heat rejection targets in a simulated application.
On these orders, Teledyne Scientific & Imaging will do the work in Thousand Oaks, Calif., and should be finished by January 2028, while HRL Laboratories will do its work in Malibu and Palo Alto, Calif.; West Lafayette, Ind.; and College Park, Md., and should be finished by August 2027.
For more information contact HRL Laboratories online at www.hrl.com; Teledyne Scientific & Imaging at www.teledyne-si.com/en-us; or DARPA at www.darpa.mil/research/programs/Minitherms3D.
