Advanced anti-tamper technologies are goal of Navy Protection of Electronics Systems solicitation

ARLINGTON, Va., 21 April 2011. U.S. Navy researchers are asking industry to develop new and innovative anti-tamper techniques to prevent potentially hostile nations or organization from reverse-engineering U.S. military-critical technology. These anti-tamper measures are intended to prevent others from transferring U.S. military technology, altering military technology, or developing countermeasures to important military systems.

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ARLINGTON, Va., 21 April 2011. U.S. Navy researchers are asking industry to develop new and innovative anti-tamper techniques to prevent potentially hostile nations or organization from reverse-engineering U.S. military-critical technology. These anti-tamper measures are intended to prevent others from transferring U.S. military technology, altering military technology, or developing countermeasures to important military systems.The U.S. Office of Naval Research (ONR) in Arlington, Va., released a broad agency announcement (ONR BAA 11-020) Monday for the Protection of Electronics Systems program to develop long-lasting undetectable layered technologies to detect attempts to tamper with U.S. and allied military technology, yet provide no indication of when it detects a tamper attempt.The program has four primary thrusts: memory erasure; high-density 3D packaging; high-density 3D electronics packaging for secure processing; and reliable physical unclonable functions.

In the first part, ONR scientists are asking industry to develop technologies able to erase data completely and irreversibly that is stored in non-volatile memory. Approaches should not use energetics or cause damage beyond the active part of the memory device. These approaches should work in the military operating temperature range of -55 to 125 degrees Celsius for 15 to 20 years with very limited electrical power.

In the second part, ONR experts want industry to enhance the performance of high-density 3D electronics packaging, such as enhanced cooling, keeping electromagnetic interference among internal components to a minimum, and shielding external electromagnetic emissions.

In the third part, Navy researchers are asking industry to develop technologies for high-density 3D electronics packaging that can integrate several commercial off-the-shelf (COTS) and custom-designed devices into a secure processing system. Packaging should contain technologies such as COTs processors, fine-pitch ball-grid arrays, DRAM and SRAM memory chips, and anti-tamper protection. These technologies should prevent reverse engineering.

In the fourth part, ONR scientists want industry to develop ways to design and install physical unclonable functions (PUFs) in field-programmable gate arrays (FPGAs) to authenticate these FPGAs and generate volatile keys for advanced encryption and decryption.

Companies interested should send white papers to ONR no later than 31 May 2011, and full proposals no later than 28 Sept. 2011. Navy officials will accept only hard copies of white papers delivered by post, by hand, or by commercial carrier to the Office of Naval Research, Attn: Mr. Chuck Cammuse, ONR Department Code: 31, 875 North Randolph St., Suite W1116C, Arlington, VA 22203-1995.

For questions or concerns contact ONR's Betsy DeLong by e-mail at betsy.delong@navy.mil; Dave Hollinberger at david.hollinberger@navy.mil, Rebecca Foster at rebecca.d.foster@navy.mil, Vera Carroll at vera.carroll@navy.mil, or Diana Pacheco at diana.pacheco@navy.mil.

More information is online at https://www.fbo.gov/spg/DON/ONR/ONR/ONRBAA11-020/listing.html.

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