This webinar was originally broadcast on November 30, 2023. Now Available On Demand!
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Commercial new space programs are increasing demand for high-reliability microelectronics, but national security concerns can limit access to U.S. based advanced semiconductor process nodes. Those attending will learn how to navigate these uncertain times through innovative microelectronics design, packaging, testing, and qualification. They will learn the latest options and best practices for cost-optimized hi-reliability microelectronics for demanding program requirements.
A high percentage of electronics bound for space or other high-reliability applications do not have Designed-for-Test (DFT) or Designed-for-Manufacture (DFM) availability, and as such would require a qualification test plan to be created to ensure the expected or extended program mission life desired, is achieved. It is more critical than ever for engineers to understand all the available high-reliability options for high-reliability programs. Potential solutions range from new application-specific integrated circuit (ASIC) development, to upscreening and plastic-encapsulated module (PEM) qualification of existing devices. This seminar will help engineers, program managers, and subcontractors better understand high-reliability device requirements of MIL-PRF-38535, -38534, and other qualifications and requirements, to best define the appropriate testing and qualification plan needed to meet the program’s expected mission life and budget.
Topics will cover requirements for:
- electrical testing compliance over voltage and temperature, lead-time, costs, coverage and impacts to reliability
- component complexity, test compliance, test time, junction or case temperature, reliability concerns sourcing large mix low volume BOMs,
- detecting defects at wafer probe, burn-in, electrical test, package assembly, and environmental testing that affect reliability
- other design and testing requirements for hi-rel microelectronics.
Mario Saucedo | General Manager, Micross Silicon Turnkey Solutions | Micross STS
With over 20 years of experience in driving new product and technologies in the microelectronics and semiconductor industry, Mario’s subject matter expertise spans all areas of strategic planning, R&D, operations, and business development. Mario has extensive experience in the telecommunications, industrial, defense, and space markets, with delivering engineering solutions for high-reliability applications. Most recently during his tenure at Skyworks Solutions, a leader in RF semiconductor solutions, Mario championed growth within the defense and space markets by utilizing Skyworks extensive IP and manufacturing prowess to provide breakthrough high-reliability products. Mario is the General Manager at the Micross STS facility in Milpitas, CA, helping customers bring their products into hi-reliability applications, by leveraging Micross engineering expertise and advance test and assembly capabilities.
Ron Erickson | Chief Engineer, Micross Silicon Turnkey Solutions | Micross STS
Ron is an expert in Hi-Rel microelectronics electrical test, with a career spanning 22 years where he was directly responsible for new product development in test, product, and managing test, product, integrated circuit packaging, and design lab product validation engineering teams. Ron has completed microelectronic developments with requirements under designations of ITAR, Secret, and Industrial for products that must perform reliably in harsh environments. Ron has an extensive microelectronics background and understands the Hi-Rel device requirements to successfully complete MIL-PRF-38535, -38534, PEM, and varying SCD, or AID specific qualifications. Hi-Rel microelectronics require specific development attributes of 100% electrical testing compliance over all corners of voltage and temperature, and these requirements vary from commercial products in complexity, coverage, test time, small lot statistical analysis, and mission reliability. Ron is the Chief Engineer at Micross Silicon Turnkey Solutions at the Micross facility in Milpitas, CA, responsible for the development of microelectronic processes, beginning with wafer test, IC packaging, package test, burn-in, and environmental test activities, through completion of successful qualification.